{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "sck register register reg32\[30\] reg32\[29\] 275.03 MHz Internal " "Info: Clock \"sck\" Internal fmax is restricted to 275.03 MHz between source register \"reg32\[30\]\" and destination register \"reg32\[29\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.897 ns + Longest register register " "Info: + Longest register to register delay is 1.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg32\[30\] 1 REG LC_X12_Y9_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y9_N4; Fanout = 4; REG Node = 'reg32\[30\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { reg32[30] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.782 ns) + CELL(0.115 ns) 1.897 ns reg32\[29\] 2 REG LC_X16_Y8_N9 4 " "Info: 2: + IC(1.782 ns) + CELL(0.115 ns) = 1.897 ns; Loc. = LC_X16_Y8_N9; Fanout = 4; REG Node = 'reg32\[29\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.897 ns" { reg32[30] reg32[29] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 6.06 % ) " "Info: Total cell delay = 0.115 ns ( 6.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.782 ns ( 93.94 % ) " "Info: Total interconnect delay = 1.782 ns ( 93.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.897 ns" { reg32[30] reg32[29] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.897 ns" { reg32[30] reg32[29] } { 0.000ns 1.782ns } { 0.000ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.015 ns - Smallest " "Info: - Smallest clock skew is 0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sck destination 6.664 ns + Shortest register " "Info: + Shortest clock path from clock \"sck\" to destination register is 6.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sck 1 CLK PIN_132 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_132; Fanout = 32; CLK Node = 'sck'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sck } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.478 ns) + CELL(0.711 ns) 6.664 ns reg32\[29\] 2 REG LC_X16_Y8_N9 4 " "Info: 2: + IC(4.478 ns) + CELL(0.711 ns) = 6.664 ns; Loc. = LC_X16_Y8_N9; Fanout = 4; REG Node = 'reg32\[29\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.189 ns" { sck reg32[29] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 32.80 % ) " "Info: Total cell delay = 2.186 ns ( 32.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.478 ns ( 67.20 % ) " "Info: Total interconnect delay = 4.478 ns ( 67.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.664 ns" { sck reg32[29] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.664 ns" { sck sck~out0 reg32[29] } { 0.000ns 0.000ns 4.478ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sck source 6.649 ns - Longest register " "Info: - Longest clock path from clock \"sck\" to source register is 6.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sck 1 CLK PIN_132 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_132; Fanout = 32; CLK Node = 'sck'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sck } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.463 ns) + CELL(0.711 ns) 6.649 ns reg32\[30\] 2 REG LC_X12_Y9_N4 4 " "Info: 2: + IC(4.463 ns) + CELL(0.711 ns) = 6.649 ns; Loc. = LC_X12_Y9_N4; Fanout = 4; REG Node = 'reg32\[30\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.174 ns" { sck reg32[30] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 32.88 % ) " "Info: Total cell delay = 2.186 ns ( 32.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.463 ns ( 67.12 % ) " "Info: Total interconnect delay = 4.463 ns ( 67.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { sck reg32[30] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { sck sck~out0 reg32[30] } { 0.000ns 0.000ns 4.463ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.664 ns" { sck reg32[29] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.664 ns" { sck sck~out0 reg32[29] } { 0.000ns 0.000ns 4.478ns } { 0.000ns 1.475ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { sck reg32[30] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { sck sck~out0 reg32[30] } { 0.000ns 0.000ns 4.463ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.897 ns" { reg32[30] reg32[29] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.897 ns" { reg32[30] reg32[29] } { 0.000ns 1.782ns } { 0.000ns 0.115ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.664 ns" { sck reg32[29] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.664 ns" { sck sck~out0 reg32[29] } { 0.000ns 0.000ns 4.478ns } { 0.000ns 1.475ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { sck reg32[30] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { sck sck~out0 reg32[30] } { 0.000ns 0.000ns 4.463ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { reg32[29] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { reg32[29] } {  } {  } "" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll20:u1\|altpll:altpll_component\|_clk0 register cnt\[7\] register cnt\[7\] 1.323 ns " "Info: Minimum slack time is 1.323 ns for clock \"pll20:u1\|altpll:altpll_component\|_clk0\" between source register \"cnt\[7\]\" and destination register \"cnt\[7\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.114 ns + Shortest register register " "Info: + Shortest register to register delay is 1.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[7\] 1 REG LC_X16_Y11_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y11_N8; Fanout = 3; REG Node = 'cnt\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[7] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.507 ns) + CELL(0.607 ns) 1.114 ns cnt\[7\] 2 REG LC_X16_Y11_N8 3 " "Info: 2: + IC(0.507 ns) + CELL(0.607 ns) = 1.114 ns; Loc. = LC_X16_Y11_N8; Fanout = 3; REG Node = 'cnt\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { cnt[7] cnt[7] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 54.49 % ) " "Info: Total cell delay = 0.607 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.507 ns ( 45.51 % ) " "Info: Total interconnect delay = 0.507 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { cnt[7] cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.114 ns" { cnt[7] cnt[7] } { 0.000ns 0.507ns } { 0.000ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.833 ns " "Info: + Latch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll20:u1\|altpll:altpll_component\|_clk0 5.555 ns -1.833 ns  50 " "Info: Clock period of Destination clock \"pll20:u1\|altpll:altpll_component\|_clk0\" is 5.555 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll20:u1\|altpll:altpll_component\|_clk0 5.555 ns -1.833 ns  50 " "Info: Clock period of Source clock \"pll20:u1\|altpll:altpll_component\|_clk0\" is 5.555 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll20:u1\|altpll:altpll_component\|_clk0 destination 2.318 ns + Longest register " "Info: + Longest clock path from clock \"pll20:u1\|altpll:altpll_component\|_clk0\" to destination register is 2.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll20:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'pll20:u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll20:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.711 ns) 2.318 ns cnt\[7\] 2 REG LC_X16_Y11_N8 3 " "Info: 2: + IC(1.607 ns) + CELL(0.711 ns) = 2.318 ns; Loc. = LC_X16_Y11_N8; Fanout = 3; REG Node = 'cnt\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.67 % ) " "Info: Total cell delay = 0.711 ns ( 30.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.33 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll20:u1\|altpll:altpll_component\|_clk0 source 2.318 ns - Shortest register " "Info: - Shortest clock path from clock \"pll20:u1\|altpll:altpll_component\|_clk0\" to source register is 2.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll20:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'pll20:u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll20:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.711 ns) 2.318 ns cnt\[7\] 2 REG LC_X16_Y11_N8 3 " "Info: 2: + IC(1.607 ns) + CELL(0.711 ns) = 2.318 ns; Loc. = LC_X16_Y11_N8; Fanout = 3; REG Node = 'cnt\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.67 % ) " "Info: Total cell delay = 0.711 ns ( 30.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.33 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { cnt[7] cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.114 ns" { cnt[7] cnt[7] } { 0.000ns 0.507ns } { 0.000ns 0.607ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[7] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "reg32\[31\] sda sck 0.828 ns register " "Info: tsu for register \"reg32\[31\]\" (data pin = \"sda\", clock pin = \"sck\") is 0.828 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.440 ns + Longest pin register " "Info: + Longest pin to register delay is 7.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sda 1 PIN PIN_131 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_131; Fanout = 1; PIN Node = 'sda'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.850 ns) + CELL(0.115 ns) 7.440 ns reg32\[31\] 2 REG LC_X12_Y9_N2 4 " "Info: 2: + IC(5.850 ns) + CELL(0.115 ns) = 7.440 ns; Loc. = LC_X12_Y9_N2; Fanout = 4; REG Node = 'reg32\[31\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.965 ns" { sda reg32[31] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 21.37 % ) " "Info: Total cell delay = 1.590 ns ( 21.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.850 ns ( 78.63 % ) " "Info: Total interconnect delay = 5.850 ns ( 78.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.440 ns" { sda reg32[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.440 ns" { sda sda~out0 reg32[31] } { 0.000ns 0.000ns 5.850ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sck destination 6.649 ns - Shortest register " "Info: - Shortest clock path from clock \"sck\" to destination register is 6.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sck 1 CLK PIN_132 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_132; Fanout = 32; CLK Node = 'sck'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sck } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.463 ns) + CELL(0.711 ns) 6.649 ns reg32\[31\] 2 REG LC_X12_Y9_N2 4 " "Info: 2: + IC(4.463 ns) + CELL(0.711 ns) = 6.649 ns; Loc. = LC_X12_Y9_N2; Fanout = 4; REG Node = 'reg32\[31\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.174 ns" { sck reg32[31] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 32.88 % ) " "Info: Total cell delay = 2.186 ns ( 32.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.463 ns ( 67.12 % ) " "Info: Total interconnect delay = 4.463 ns ( 67.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { sck reg32[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { sck sck~out0 reg32[31] } { 0.000ns 0.000ns 4.463ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.440 ns" { sda reg32[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.440 ns" { sda sda~out0 reg32[31] } { 0.000ns 0.000ns 5.850ns } { 0.000ns 1.475ns 0.115ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { sck reg32[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { sck sck~out0 reg32[31] } { 0.000ns 0.000ns 4.463ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk output\[1\] Ram0~16 9.778 ns register " "Info: tco from clock \"clk\" to destination pin \"output\[1\]\" through register \"Ram0~16\" is 9.778 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk pll20:u1\|altpll:altpll_component\|_clk0 -1.833 ns + " "Info: + Offset between input clock \"clk\" and output clock \"pll20:u1\|altpll:altpll_component\|_clk0\" is -1.833 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 8 -1 0 } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll20:u1\|altpll:altpll_component\|_clk0 source 2.318 ns + Longest register " "Info: + Longest clock path from clock \"pll20:u1\|altpll:altpll_component\|_clk0\" to source register is 2.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll20:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'pll20:u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll20:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.711 ns) 2.318 ns Ram0~16 2 REG LC_X16_Y8_N4 28 " "Info: 2: + IC(1.607 ns) + CELL(0.711 ns) = 2.318 ns; Loc. = LC_X16_Y8_N4; Fanout = 28; REG Node = 'Ram0~16'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~16 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.67 % ) " "Info: Total cell delay = 0.711 ns ( 30.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.33 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~16 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~16 } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.069 ns + Longest register pin " "Info: + Longest register to pin delay is 9.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Ram0~16 1 REG LC_X16_Y8_N4 28 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y8_N4; Fanout = 28; REG Node = 'Ram0~16'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Ram0~16 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.239 ns) + CELL(0.590 ns) 3.829 ns Ram0~1568 2 COMB LC_X25_Y2_N4 1 " "Info: 2: + IC(3.239 ns) + CELL(0.590 ns) = 3.829 ns; Loc. = LC_X25_Y2_N4; Fanout = 1; COMB Node = 'Ram0~1568'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.829 ns" { Ram0~16 Ram0~1568 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 4.564 ns Ram0~1570 3 COMB LC_X25_Y2_N6 1 " "Info: 3: + IC(0.443 ns) + CELL(0.292 ns) = 4.564 ns; Loc. = LC_X25_Y2_N6; Fanout = 1; COMB Node = 'Ram0~1570'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { Ram0~1568 Ram0~1570 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.590 ns) 5.584 ns Ram0~1572 4 COMB LC_X25_Y2_N2 1 " "Info: 4: + IC(0.430 ns) + CELL(0.590 ns) = 5.584 ns; Loc. = LC_X25_Y2_N2; Fanout = 1; COMB Node = 'Ram0~1572'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.020 ns" { Ram0~1570 Ram0~1572 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.361 ns) + CELL(2.124 ns) 9.069 ns output\[1\] 5 PIN PIN_75 0 " "Info: 5: + IC(1.361 ns) + CELL(2.124 ns) = 9.069 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'output\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.485 ns" { Ram0~1572 output[1] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.596 ns ( 39.65 % ) " "Info: Total cell delay = 3.596 ns ( 39.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.473 ns ( 60.35 % ) " "Info: Total interconnect delay = 5.473 ns ( 60.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.069 ns" { Ram0~16 Ram0~1568 Ram0~1570 Ram0~1572 output[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.069 ns" { Ram0~16 Ram0~1568 Ram0~1570 Ram0~1572 output[1] } { 0.000ns 3.239ns 0.443ns 0.430ns 1.361ns } { 0.000ns 0.590ns 0.292ns 0.590ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~16 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~16 } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.069 ns" { Ram0~16 Ram0~1568 Ram0~1570 Ram0~1572 output[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.069 ns" { Ram0~16 Ram0~1568 Ram0~1570 Ram0~1572 output[1] } { 0.000ns 3.239ns 0.443ns 0.430ns 1.361ns } { 0.000ns 0.590ns 0.292ns 0.590ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}