{ "Info" "ITDB_TH_RESULT" "reg32\[31\] sda sck -0.776 ns register " "Info: th for register \"reg32\[31\]\" (data pin = \"sda\", clock pin = \"sck\") is -0.776 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sck destination 6.649 ns + Longest register " "Info: + Longest clock path from clock \"sck\" to destination register is 6.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sck 1 CLK PIN_132 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_132; Fanout = 32; CLK Node = 'sck'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sck } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.463 ns) + CELL(0.711 ns) 6.649 ns reg32\[31\] 2 REG LC_X12_Y9_N2 4 " "Info: 2: + IC(4.463 ns) + CELL(0.711 ns) = 6.649 ns; Loc. = LC_X12_Y9_N2; Fanout = 4; REG Node = 'reg32\[31\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.174 ns" { sck reg32[31] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 32.88 % ) " "Info: Total cell delay = 2.186 ns ( 32.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.463 ns ( 67.12 % ) " "Info: Total interconnect delay = 4.463 ns ( 67.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { sck reg32[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { sck sck~out0 reg32[31] } { 0.000ns 0.000ns 4.463ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.440 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sda 1 PIN PIN_131 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_131; Fanout = 1; PIN Node = 'sda'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.850 ns) + CELL(0.115 ns) 7.440 ns reg32\[31\] 2 REG LC_X12_Y9_N2 4 " "Info: 2: + IC(5.850 ns) + CELL(0.115 ns) = 7.440 ns; Loc. = LC_X12_Y9_N2; Fanout = 4; REG Node = 'reg32\[31\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.965 ns" { sda reg32[31] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 21.37 % ) " "Info: Total cell delay = 1.590 ns ( 21.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.850 ns ( 78.63 % ) " "Info: Total interconnect delay = 5.850 ns ( 78.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.440 ns" { sda reg32[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.440 ns" { sda sda~out0 reg32[31] } { 0.000ns 0.000ns 5.850ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { sck reg32[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { sck sck~out0 reg32[31] } { 0.000ns 0.000ns 4.463ns } { 0.000ns 1.475ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.440 ns" { sda reg32[31] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.440 ns" { sda sda~out0 reg32[31] } { 0.000ns 0.000ns 5.850ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 28 20:40:56 2007 " "Info: Processing ended: Tue Aug 28 20:40:56 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}