Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Aug 28 20:40:20 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ledwater -c ledwater
Info: Selected device EP1C3T144C8 for design "ledwater"
Info: Implementing parameter values for PLL "pll20:u1|altpll:altpll_component|pll"
    Info: Implementing clock multiplication of 9, clock division of 1, and phase shift of 0 degrees (0 ps) for pll20:u1|altpll:altpll_component|_clk0 port
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 129 of 129 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 12
    Info: Pin ~ASDO~ is reserved at location 25
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Promoted PLL clock signals
    Info: Promoted signal "pll20:u1|altpll:altpll_component|_clk0" to use global clock (user assigned)
Info: Completed PLL Placement Operation
Info: Automatically promoted signal "sck" to use Global clock
Info: Pin "sck" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Warning: Output port clk0 of PLL "pll20:u1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "key_data[0]" is assigned to location or region, but does not exist in design
    Warning: Node "key_data[1]" is assigned to location or region, but does not exist in design
    Warning: Node "key_data[2]" is assigned to location or region, but does not exist in design
    Warning: Node "key_data[3]" is assigned to location or region, but does not exist in design
    Warning: Node "key_int" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 3.168 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y11; Fanout = 3; REG Node = 'cnt[0]'
    Info: 2: + IC(0.461 ns) + CELL(0.575 ns) = 1.036 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'cnt[0]~165COUT1'
    Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.116 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'cnt[1]~164COUT1'
    Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.196 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'cnt[2]~163COUT1'
    Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.454 ns; Loc. = LAB_X16_Y11; Fanout = 6; COMB Node = 'cnt[3]~162'
    Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.590 ns; Loc. = LAB_X16_Y11; Fanout = 6; COMB Node = 'cnt[8]~157'
    Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.726 ns; Loc. = LAB_X16_Y10; Fanout = 6; COMB Node = 'cnt[13]~152'
    Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 1.862 ns; Loc. = LAB_X16_Y10; Fanout = 6; COMB Node = 'cnt[18]~147'
    Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 1.998 ns; Loc. = LAB_X16_Y9; Fanout = 6; COMB Node = 'cnt[23]~142'
    Info: 10: + IC(0.000 ns) + CELL(0.136 ns) = 2.134 ns; Loc. = LAB_X16_Y9; Fanout = 6; COMB Node = 'cnt[28]~137'
    Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 2.270 ns; Loc. = LAB_X16_Y8; Fanout = 4; COMB Node = 'Ram0~1556'
    Info: 12: + IC(0.000 ns) + CELL(0.898 ns) = 3.168 ns; Loc. = LAB_X16_Y8; Fanout = 21; REG Node = 'Ram0~20'
    Info: Total cell delay = 2.707 ns ( 85.45 % )
    Info: Total interconnect delay = 0.461 ns ( 14.55 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 8 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Tue Aug 28 20:40:33 2007
    Info: Elapsed time: 00:00:13