?? mc68hc908jb16.h
字號:
#define T1MODL_BIT0_MASK 1
#define T1MODL_BIT0_BITNUM 0
#define T1MODL_BIT1_MASK 2
#define T1MODL_BIT1_BITNUM 1
#define T1MODL_BIT2_MASK 4
#define T1MODL_BIT2_BITNUM 2
#define T1MODL_BIT3_MASK 8
#define T1MODL_BIT3_BITNUM 3
#define T1MODL_BIT4_MASK 16
#define T1MODL_BIT4_BITNUM 4
#define T1MODL_BIT5_MASK 32
#define T1MODL_BIT5_BITNUM 5
#define T1MODL_BIT6_MASK 64
#define T1MODL_BIT6_BITNUM 6
#define T1MODL_BIT7_MASK 128
#define T1MODL_BIT7_BITNUM 7
#define T1MODL_BIT_MASK 255
#define T1MODL_BIT_BITNUM 0
} Overlap_STR;
struct {
word grpBIT :16;
} MergedBits;
} T1MODSTR;
extern volatile T1MODSTR _T1MOD @0x0000000E;
#define T1MOD _T1MOD.Word
#define T1MOD_BIT _T1MOD.MergedBits.grpBIT
#define T1MOD_BIT_MASK 65535
#define T1MOD_BIT_BITNUM 0
/*** T1SC0 - TIM Channel 0 Status and Control Register; 0x00000010 ***/
typedef union {
byte Byte;
struct {
byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */
byte TOV0 :1; /* Toggle-On-Overflow Bit */
byte ELS0A :1; /* Edge/Level Select Bit */
byte ELS0B :1; /* Edge/Level Select Bit */
byte MS0A :1; /* Mode Select Bit A */
byte MS0B :1; /* Mode Select Bit B */
byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */
byte CH0F :1; /* Channel 0 Flag Bit */
} Bits;
struct {
byte :1;
byte grpTOV :1;
byte :1;
byte :1;
byte grpMS0x :2;
byte :1;
byte :1;
} MergedBits;
} T1SC0STR;
extern volatile T1SC0STR _T1SC0 @0x00000010;
#define T1SC0 _T1SC0.Byte
#define T1SC0_CH0MAX _T1SC0.Bits.CH0MAX
#define T1SC0_TOV0 _T1SC0.Bits.TOV0
#define T1SC0_ELS0A _T1SC0.Bits.ELS0A
#define T1SC0_ELS0B _T1SC0.Bits.ELS0B
#define T1SC0_MS0A _T1SC0.Bits.MS0A
#define T1SC0_MS0B _T1SC0.Bits.MS0B
#define T1SC0_CH0IE _T1SC0.Bits.CH0IE
#define T1SC0_CH0F _T1SC0.Bits.CH0F
#define T1SC0_MS0x _T1SC0.MergedBits.grpMS0x
#define T1SC0_CH0MAX_MASK 1
#define T1SC0_CH0MAX_BITNUM 0
#define T1SC0_TOV0_MASK 2
#define T1SC0_TOV0_BITNUM 1
#define T1SC0_ELS0A_MASK 4
#define T1SC0_ELS0A_BITNUM 2
#define T1SC0_ELS0B_MASK 8
#define T1SC0_ELS0B_BITNUM 3
#define T1SC0_MS0A_MASK 16
#define T1SC0_MS0A_BITNUM 4
#define T1SC0_MS0B_MASK 32
#define T1SC0_MS0B_BITNUM 5
#define T1SC0_CH0IE_MASK 64
#define T1SC0_CH0IE_BITNUM 6
#define T1SC0_CH0F_MASK 128
#define T1SC0_CH0F_BITNUM 7
#define T1SC0_MS0x_MASK 48
#define T1SC0_MS0x_BITNUM 4
/*** T1CH0 - TIM Channel 0 Register; 0x00000011 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T1CH0H - TIM Channel 0 Register High; 0x00000011 ***/
union {
byte Byte;
struct {
byte BIT8 :1; /* TIM1 Channel Register BIT 8 */
byte BIT9 :1; /* TIM1 Channel Register BIT 9 */
byte BIT10 :1; /* TIM1 Channel Register BIT 10 */
byte BIT11 :1; /* TIM1 Channel Register BIT 11 */
byte BIT12 :1; /* TIM1 Channel Register BIT 12 */
byte BIT13 :1; /* TIM1 Channel Register BIT 13 */
byte BIT14 :1; /* TIM1 Channel Register BIT 14 */
byte BIT15 :1; /* TIM1 Channel Register BIT 15 */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T1CH0HSTR;
#define T1CH0H _T1CH0.Overlap_STR.T1CH0HSTR.Byte
#define T1CH0H_BIT8 _T1CH0.Overlap_STR.T1CH0HSTR.Bits.BIT8
#define T1CH0H_BIT9 _T1CH0.Overlap_STR.T1CH0HSTR.Bits.BIT9
#define T1CH0H_BIT10 _T1CH0.Overlap_STR.T1CH0HSTR.Bits.BIT10
#define T1CH0H_BIT11 _T1CH0.Overlap_STR.T1CH0HSTR.Bits.BIT11
#define T1CH0H_BIT12 _T1CH0.Overlap_STR.T1CH0HSTR.Bits.BIT12
#define T1CH0H_BIT13 _T1CH0.Overlap_STR.T1CH0HSTR.Bits.BIT13
#define T1CH0H_BIT14 _T1CH0.Overlap_STR.T1CH0HSTR.Bits.BIT14
#define T1CH0H_BIT15 _T1CH0.Overlap_STR.T1CH0HSTR.Bits.BIT15
#define T1CH0H_BIT_8 _T1CH0.Overlap_STR.T1CH0HSTR.MergedBits.grpBIT_8
#define T1CH0H_BIT T1CH0H_BIT_8
#define T1CH0H_BIT8_MASK 1
#define T1CH0H_BIT8_BITNUM 0
#define T1CH0H_BIT9_MASK 2
#define T1CH0H_BIT9_BITNUM 1
#define T1CH0H_BIT10_MASK 4
#define T1CH0H_BIT10_BITNUM 2
#define T1CH0H_BIT11_MASK 8
#define T1CH0H_BIT11_BITNUM 3
#define T1CH0H_BIT12_MASK 16
#define T1CH0H_BIT12_BITNUM 4
#define T1CH0H_BIT13_MASK 32
#define T1CH0H_BIT13_BITNUM 5
#define T1CH0H_BIT14_MASK 64
#define T1CH0H_BIT14_BITNUM 6
#define T1CH0H_BIT15_MASK 128
#define T1CH0H_BIT15_BITNUM 7
#define T1CH0H_BIT_8_MASK 255
#define T1CH0H_BIT_8_BITNUM 0
/*** T1CH0L - TIM Channel 0 Register Low; 0x00000012 ***/
union {
byte Byte;
struct {
byte BIT0 :1; /* TIM1 Channel Register BIT 0 */
byte BIT1 :1; /* TIM1 Channel Register BIT 1 */
byte BIT2 :1; /* TIM1 Channel Register BIT 2 */
byte BIT3 :1; /* TIM1 Channel Register BIT 3 */
byte BIT4 :1; /* TIM1 Channel Register BIT 4 */
byte BIT5 :1; /* TIM1 Channel Register BIT 5 */
byte BIT6 :1; /* TIM1 Channel Register BIT 6 */
byte BIT7 :1; /* TIM1 Channel Register BIT 7 */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T1CH0LSTR;
#define T1CH0L _T1CH0.Overlap_STR.T1CH0LSTR.Byte
#define T1CH0L_BIT0 _T1CH0.Overlap_STR.T1CH0LSTR.Bits.BIT0
#define T1CH0L_BIT1 _T1CH0.Overlap_STR.T1CH0LSTR.Bits.BIT1
#define T1CH0L_BIT2 _T1CH0.Overlap_STR.T1CH0LSTR.Bits.BIT2
#define T1CH0L_BIT3 _T1CH0.Overlap_STR.T1CH0LSTR.Bits.BIT3
#define T1CH0L_BIT4 _T1CH0.Overlap_STR.T1CH0LSTR.Bits.BIT4
#define T1CH0L_BIT5 _T1CH0.Overlap_STR.T1CH0LSTR.Bits.BIT5
#define T1CH0L_BIT6 _T1CH0.Overlap_STR.T1CH0LSTR.Bits.BIT6
#define T1CH0L_BIT7 _T1CH0.Overlap_STR.T1CH0LSTR.Bits.BIT7
#define T1CH0L_BIT _T1CH0.Overlap_STR.T1CH0LSTR.MergedBits.grpBIT
#define T1CH0L_BIT0_MASK 1
#define T1CH0L_BIT0_BITNUM 0
#define T1CH0L_BIT1_MASK 2
#define T1CH0L_BIT1_BITNUM 1
#define T1CH0L_BIT2_MASK 4
#define T1CH0L_BIT2_BITNUM 2
#define T1CH0L_BIT3_MASK 8
#define T1CH0L_BIT3_BITNUM 3
#define T1CH0L_BIT4_MASK 16
#define T1CH0L_BIT4_BITNUM 4
#define T1CH0L_BIT5_MASK 32
#define T1CH0L_BIT5_BITNUM 5
#define T1CH0L_BIT6_MASK 64
#define T1CH0L_BIT6_BITNUM 6
#define T1CH0L_BIT7_MASK 128
#define T1CH0L_BIT7_BITNUM 7
#define T1CH0L_BIT_MASK 255
#define T1CH0L_BIT_BITNUM 0
} Overlap_STR;
struct {
word grpBIT :16;
} MergedBits;
} T1CH0STR;
extern volatile T1CH0STR _T1CH0 @0x00000011;
#define T1CH0 _T1CH0.Word
#define T1CH0_BIT _T1CH0.MergedBits.grpBIT
#define T1CH0_BIT_MASK 65535
#define T1CH0_BIT_BITNUM 0
/*** T1SC1 - TIM Channel 1 Status and Control Register; 0x00000013 ***/
typedef union {
byte Byte;
struct {
byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */
byte TOV1 :1; /* Toggle-On-Overflow Bit */
byte ELS1A :1; /* Edge/Level Select Bit */
byte ELS1B :1; /* Edge/Level Select Bit */
byte MS1A :1; /* Mode Select Bit A */
byte :1;
byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */
byte CH1F :1; /* Channel 1 Flag Bit */
} Bits;
} T1SC1STR;
extern volatile T1SC1STR _T1SC1 @0x00000013;
#define T1SC1 _T1SC1.Byte
#define T1SC1_CH1MAX _T1SC1.Bits.CH1MAX
#define T1SC1_TOV1 _T1SC1.Bits.TOV1
#define T1SC1_ELS1A _T1SC1.Bits.ELS1A
#define T1SC1_ELS1B _T1SC1.Bits.ELS1B
#define T1SC1_MS1A _T1SC1.Bits.MS1A
#define T1SC1_CH1IE _T1SC1.Bits.CH1IE
#define T1SC1_CH1F _T1SC1.Bits.CH1F
#define T1SC1_CH1MAX_MASK 1
#define T1SC1_CH1MAX_BITNUM 0
#define T1SC1_TOV1_MASK 2
#define T1SC1_TOV1_BITNUM 1
#define T1SC1_ELS1A_MASK 4
#define T1SC1_ELS1A_BITNUM 2
#define T1SC1_ELS1B_MASK 8
#define T1SC1_ELS1B_BITNUM 3
#define T1SC1_MS1A_MASK 16
#define T1SC1_MS1A_BITNUM 4
#define T1SC1_CH1IE_MASK 64
#define T1SC1_CH1IE_BITNUM 6
#define T1SC1_CH1F_MASK 128
#define T1SC1_CH1F_BITNUM 7
/*** T1CH1 - TIM Channel 1 Register; 0x00000014 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T1CH1H - TIM Channel 1 Register High; 0x00000014 ***/
union {
byte Byte;
struct {
byte BIT8 :1; /* TIM1 Channel Register BIT 8 */
byte BIT9 :1; /* TIM1 Channel Register BIT 9 */
byte BIT10 :1; /* TIM1 Channel Register BIT 10 */
byte BIT11 :1; /* TIM1 Channel Register BIT 11 */
byte BIT12 :1; /* TIM1 Channel Register BIT 12 */
byte BIT13 :1; /* TIM1 Channel Register BIT 13 */
byte BIT14 :1; /* TIM1 Channel Register BIT 14 */
byte BIT15 :1; /* TIM1 Channel Register BIT 15 */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T1CH1HSTR;
#define T1CH1H _T1CH1.Overlap_STR.T1CH1HSTR.Byte
#define T1CH1H_BIT8 _T1CH1.Overlap_STR.T1CH1HSTR.Bits.BIT8
#define T1CH1H_BIT9 _T1CH1.Overlap_STR.T1CH1HSTR.Bits.BIT9
#define T1CH1H_BIT10 _T1CH1.Overlap_STR.T1CH1HSTR.Bits.BIT10
#define T1CH1H_BIT11 _T1CH1.Overlap_STR.T1CH1HSTR.Bits.BIT11
#define T1CH1H_BIT12 _T1CH1.Overlap_STR.T1CH1HSTR.Bits.BIT12
#define T1CH1H_BIT13 _T1CH1.Overlap_STR.T1CH1HSTR.Bits.BIT13
#define T1CH1H_BIT14 _T1CH1.Overlap_STR.T1CH1HSTR.Bits.BIT14
#define T1CH1H_BIT15 _T1CH1.Overlap_STR.T1CH1HSTR.Bits.BIT15
#define T1CH1H_BIT_8 _T1CH1.Overlap_STR.T1CH1HSTR.MergedBits.grpBIT_8
#define T1CH1H_BIT T1CH1H_BIT_8
#define T1CH1H_BIT8_MASK 1
#define T1CH1H_BIT8_BITNUM 0
#define T1CH1H_BIT9_MASK 2
#define T1CH1H_BIT9_BITNUM 1
#define T1CH1H_BIT10_MASK 4
#define T1CH1H_BIT10_BITNUM 2
#define T1CH1H_BIT11_MASK 8
#define T1CH1H_BIT11_BITNUM 3
#define T1CH1H_BIT12_MASK 16
#define T1CH1H_BIT12_BITNUM 4
#define T1CH1H_BIT13_MASK 32
#define T1CH1H_BIT13_BITNUM 5
#define T1CH1H_BIT14_MASK 64
#define T1CH1H_BIT14_BITNUM 6
#define T1CH1H_BIT15_MASK 128
#define T1CH1H_BIT15_BITNUM 7
#define T1CH1H_BIT_8_MASK 255
#define T1CH1H_BIT_8_BITNUM 0
/*** T1CH1L - TIM Channel 1 Register Low; 0x00000015 ***/
union {
byte Byte;
struct {
byte BIT0 :1; /* TIM1 Channel Register BIT 0 */
byte BIT1 :1; /* TIM1 Channel Register BIT 1 */
byte BIT2 :1; /* TIM1 Channel Register BIT 2 */
byte BIT3 :1; /* TIM1 Channel Register BIT 3 */
byte BIT4 :1; /* TIM1 Channel Register BIT 4 */
byte BIT5 :1; /* TIM1 Channel Register BIT 5 */
byte BIT6 :1; /* TIM1 Channel Register BIT 6 */
byte BIT7 :1; /* TIM1 Channel Register BIT 7 */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T1CH1LSTR;
#define T1CH1L _T1CH1.Overlap_STR.T1CH1LSTR.Byte
#define T1CH1L_BIT0 _T1CH1.Overlap_STR.T1CH1LSTR.Bits.BIT0
#define T1CH1L_BIT1 _T1CH1.Overlap_STR.T1CH1LSTR.Bits.BIT1
#define T1CH1L_BIT2 _T1CH1.Overlap_STR.T1CH1LSTR.Bits.BIT2
#define T1CH1L_BIT3 _T1CH1.Overlap_STR.T1CH1LSTR.Bits.BIT3
#define T1CH1L_BIT4 _T1CH1.Overlap_STR.T1CH1LSTR.Bits.BIT4
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -