?? mc68hc908jb16.c
字號:
/* Based on CPU DB MC68HC908JB16, version 2.89.005 (RegistersPrg V1.061) */
/* DataSheet : manual revision not specified */
#include "MC68HC908JB16.h"
/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */
volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register */
volatile BSRSTR _BSR; /* Break Status Register */
volatile CONFIGSTR _CONFIG; /* Configuration Register */
volatile COPCTLSTR _COPCTL; /* COP Control Register */
volatile DDRASTR _DDRA; /* Data Direction Register A */
volatile DDRCSTR _DDRC; /* Data Direction Register C */
volatile DDRDSTR _DDRD; /* Data Direction Register D */
volatile DDRESTR _DDRE; /* Data Direction Register E */
volatile FLBPRSTR _FLBPR; /* FLASH Block Protect Register */
volatile FLCRSTR _FLCR; /* FLASH Control Register */
volatile INT1STR _INT1; /* Interrupt Status Register 1 */
volatile INT2STR _INT2; /* Interrupt Status Register 2 */
volatile IOCRSTR _IOCR; /* IRQ Option Register */
volatile ISCRSTR _ISCR; /* IRQ Status and Control Register */
volatile KBIERSTR _KBIER; /* Keyboard Interrrupt Enable Register KBIER */
volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register */
volatile PBWCSTR _PBWC; /* CGM Bandwidth Control Register */
volatile PDCRSTR _PDCR; /* Phase Detector Control Register */
volatile PNRH1STR _PNRH1; /* PLL1 N & R Divider Select Register High */
volatile PNRH2STR _PNRH2; /* PLL2 N & R Divider Select Register High */
volatile PNSL1STR _PNSL1; /* PLL1 N Divider Select Register Low */
volatile PNSL2STR _PNSL2; /* PLL2 N Divider Select Register Low */
volatile POCRSTR _POCR; /* Port Option Control Register */
volatile PRSL1STR _PRSL1; /* PLL1 R Divider Select Register Low */
volatile PRSL2STR _PRSL2; /* PLL2 R Divider Select Register Low */
volatile PTASTR _PTA; /* Port A Data Register */
volatile PTCSTR _PTC; /* Port C Data Register */
volatile PTDSTR _PTD; /* Port D Data Register */
volatile PTESTR _PTE; /* Port E Data Register */
volatile PVCRSTR _PVCR; /* VCO Control Register */
volatile RSRSTR _RSR; /* Reset Status Register */
volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register */
volatile SCBRSTR _SCBR; /* SCI Baud Rate Register */
volatile SCC1STR _SCC1; /* SCI Control Register 1 */
volatile SCC2STR _SCC2; /* SCI Control Register 2 */
volatile SCC3STR _SCC3; /* SCI Control Register 3 */
volatile SCDRSTR _SCDR; /* SCI Data Register */
volatile SCS1STR _SCS1; /* SCI Status Register 1 */
volatile SCS2STR _SCS2; /* SCI Status Register 2 */
volatile T1SCSTR _T1SC; /* TIM Status and Control Register TSC */
volatile T1SC0STR _T1SC0; /* TIM Channel 0 Status and Control Register */
volatile T1SC1STR _T1SC1; /* TIM Channel 1 Status and Control Register */
volatile T2SCSTR _T2SC; /* TIM2 Status and Control Register TSC */
volatile T2SC0STR _T2SC0; /* TIM2 Channel 0 Status and Control Register */
volatile T2SC1STR _T2SC1; /* TIM2 Channel 1 Status and Control Register */
volatile UADDRSTR _UADDR; /* USB Address Register */
volatile UCR0STR _UCR0; /* USB Control Register 0 */
volatile UCR1STR _UCR1; /* USB Control Register 1 */
volatile UCR2STR _UCR2; /* USB Control Register 2 */
volatile UCR3STR _UCR3; /* USB Control Register 3 */
volatile UCR4STR _UCR4; /* USB Control Register 4 */
volatile UE0D0STR _UE0D0; /* USB Endpoint 0 Data Register 0 */
volatile UE0D1STR _UE0D1; /* USB Endpoint 0 Data Register 1 */
volatile UE0D2STR _UE0D2; /* USB Endpoint 0 Data Register 2 */
volatile UE0D3STR _UE0D3; /* USB Endpoint 0 Data Register 3 */
volatile UE0D4STR _UE0D4; /* USB Endpoint 0 Data Register 4 */
volatile UE0D5STR _UE0D5; /* USB Endpoint 0 Data Register 5 */
volatile UE0D6STR _UE0D6; /* USB Endpoint 0 Data Register 6 */
volatile UE0D7STR _UE0D7; /* USB Endpoint 0 Data Register 7 */
volatile UE1D0STR _UE1D0; /* USB Endpoint 1 Data Register 0 */
volatile UE1D1STR _UE1D1; /* USB Endpoint 1 Data Register 1 */
volatile UE1D2STR _UE1D2; /* USB Endpoint 1 Data Register 2 */
volatile UE1D3STR _UE1D3; /* USB Endpoint 1 Data Register 3 */
volatile UE1D4STR _UE1D4; /* USB Endpoint 1 Data Register 4 */
volatile UE1D5STR _UE1D5; /* USB Endpoint 1 Data Register 5 */
volatile UE1D6STR _UE1D6; /* USB Endpoint 1 Data Register 6 */
volatile UE1D7STR _UE1D7; /* USB Endpoint 1 Data Register 7 */
volatile UE2D0STR _UE2D0; /* USB Endpoint 2 Data Register 0 */
volatile UE2D1STR _UE2D1; /* USB Endpoint 2 Data Register 1 */
volatile UE2D2STR _UE2D2; /* USB Endpoint 2 Data Register 2 */
volatile UE2D3STR _UE2D3; /* USB Endpoint 2 Data Register 3 */
volatile UE2D4STR _UE2D4; /* USB Endpoint 2 Data Register 4 */
volatile UE2D5STR _UE2D5; /* USB Endpoint 2 Data Register 5 */
volatile UE2D6STR _UE2D6; /* USB Endpoint 2 Data Register 6 */
volatile UE2D7STR _UE2D7; /* USB Endpoint 2 Data Register 7 */
volatile UIR0STR _UIR0; /* USB Interrupt Register 0 */
volatile UIR1STR _UIR1; /* USB Interrupt Register 1 */
volatile UIR2STR _UIR2; /* USB Interrupt Register 2 */
volatile USR0STR _USR0; /* USB Status Register 0 */
volatile USR1STR _USR1; /* USB Status Register 1 */
/* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */
volatile BRKSTR _BRK; /* Break Address Register */
volatile T1CNTSTR _T1CNT; /* TIM Counter Register */
volatile T1CH0STR _T1CH0; /* TIM Channel 0 Register */
volatile T1CH1STR _T1CH1; /* TIM Channel 1 Register */
volatile T1MODSTR _T1MOD; /* TIM Counter Modulo Register */
volatile T2CNTSTR _T2CNT; /* TIM2 Counter Register */
volatile T2CH0STR _T2CH0; /* TIM2 Channel 0 Register */
volatile T2CH1STR _T2CH1; /* TIM2 Channel 1 Register */
volatile T2MODSTR _T2MOD; /* TIM2 Counter Modulo Register */
/* EOF */
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -