/* *	The PCI Library -- PCI Header Structure (based on <linux/pci.h>) * *	Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz> * *	Can be freely distributed and used under the terms of the GNU GPL. *//* * Under PCI, each device has 256 bytes of configuration address space, * of which the first 64 bytes are standardized as follows: */#define PCI_VENDOR_ID		0x00	/* 16 bits */#define PCI_DEVICE_ID		0x02	/* 16 bits */#define PCI_COMMAND		0x04	/* 16 bits */#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */#define  PCI_COMMAND_DISABLE_INTx	0x400	/* PCIE: Disable INTx interrupts */#define PCI_STATUS		0x06	/* 16 bits */#define  PCI_STATUS_INTx	0x08	/* PCIE: INTx interrupt pending */#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */#define  PCI_STATUS_DEVSEL_FAST	0x000#define  PCI_STATUS_DEVSEL_MEDIUM 0x200#define  PCI_STATUS_DEVSEL_SLOW 0x400#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8					   revision */#define PCI_REVISION_ID         0x08    /* Revision ID */#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */#define PCI_CLASS_DEVICE        0x0a    /* Device class */#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */#define PCI_HEADER_TYPE		0x0e	/* 8 bits */#define  PCI_HEADER_TYPE_NORMAL	0#define  PCI_HEADER_TYPE_BRIDGE 1#define  PCI_HEADER_TYPE_CARDBUS 2#define PCI_BIST		0x0f	/* 8 bits */#define PCI_BIST_CODE_MASK	0x0f	/* Return result */#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable *//* * Base addresses specify locations in memory or I/O space. * Decoded size can be determined by writing a value of * 0xffffffff to the register, and reading it back.  Only * 1 bits are decoded. */#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */#define  PCI_BASE_ADDRESS_SPACE	0x01	/* 0 = memory, 1 = I/O */#define  PCI_BASE_ADDRESS_SPACE_IO 0x01#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */#define  PCI_BASE_ADDRESS_MEM_MASK	(~(pciaddr_t)0x0f)#define  PCI_BASE_ADDRESS_IO_MASK	(~(pciaddr_t)0x03)/* bit 1 is reserved if address_space = 1 *//* Header type 0 (normal devices) */#define PCI_CARDBUS_CIS		0x28#define PCI_SUBSYSTEM_VENDOR_ID	0x2c#define PCI_SUBSYSTEM_ID	0x2e#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */#define  PCI_ROM_ADDRESS_ENABLE	0x01#define PCI_ROM_ADDRESS_MASK	(~(pciaddr_t)0x7ff)#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry *//* 0x35-0x3b are reserved */#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */#define PCI_MIN_GNT		0x3e	/* 8 bits */#define PCI_MAX_LAT		0x3f	/* 8 bits *//* Header type 1 (PCI-to-PCI bridges) */#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */#define PCI_IO_LIMIT		0x1d#define  PCI_IO_RANGE_TYPE_MASK	0x0f	/* I/O bridging type */#define  PCI_IO_RANGE_TYPE_16	0x00#define  PCI_IO_RANGE_TYPE_32	0x01#define  PCI_IO_RANGE_MASK	~0x0f#define PCI_SEC_STATUS		0x1e	/* Secondary status register */#define PCI_MEMORY_BASE		0x20	/* Memory range behind */#define PCI_MEMORY_LIMIT	0x22#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f#define  PCI_MEMORY_RANGE_MASK	~0x0f#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */#define PCI_PREF_MEMORY_LIMIT	0x26#define  PCI_PREF_RANGE_TYPE_MASK 0x0f#define  PCI_PREF_RANGE_TYPE_32	0x00#define  PCI_PREF_RANGE_TYPE_64	0x01#define  PCI_PREF_RANGE_MASK	~0x0f#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */#define PCI_PREF_LIMIT_UPPER32	0x2c#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */#define PCI_IO_LIMIT_UPPER16	0x32/* 0x34 same as for htype 0 *//* 0x35-0x3b is reserved */#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 *//* 0x3c-0x3d are same as for htype 0 */#define PCI_BRIDGE_CONTROL	0x3e#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */#define  PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100		/* PCI-X? */#define  PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200		/* PCI-X? */#define  PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400	/* PCI-X? */#define  PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800	/* PCI-X? *//* Header type 2 (CardBus bridges) *//* 0x14-0x15 reserved */#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */#define PCI_CB_MEMORY_BASE_0	0x1c#define PCI_CB_MEMORY_LIMIT_0	0x20#define PCI_CB_MEMORY_BASE_1	0x24#define PCI_CB_MEMORY_LIMIT_1	0x28#define PCI_CB_IO_BASE_0	0x2c#define PCI_CB_IO_BASE_0_HI	0x2e#define PCI_CB_IO_LIMIT_0	0x30#define PCI_CB_IO_LIMIT_0_HI	0x32#define PCI_CB_IO_BASE_1	0x34#define PCI_CB_IO_BASE_1_HI	0x36#define PCI_CB_IO_LIMIT_1	0x38#define PCI_CB_IO_LIMIT_1_HI	0x3a#define  PCI_CB_IO_RANGE_MASK	~0x03/* 0x3c-0x3d are same as for htype 0 */#define PCI_CB_BRIDGE_CONTROL	0x3e#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */#define  PCI_CB_BRIDGE_CTL_SERR		0x02#define  PCI_CB_BRIDGE_CTL_ISA		0x04#define  PCI_CB_BRIDGE_CTL_VGA		0x08#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40#define PCI_CB_SUBSYSTEM_ID	0x42#define PCI_CB_LEGACY_MODE_BASE	0x44	/* 16-bit PC Card legacy mode base address (ExCa) *//* 0x48-0x7f reserved *//* Capability lists */#define PCI_CAP_LIST_ID		0	/* Capability ID */#define  PCI_CAP_ID_PM		0x01	/* Power Management */#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */#define  PCI_CAP_ID_HT          0x08    /* HyperTransport */#define  PCI_CAP_ID_VNDR	0x09	/* Vendor specific */#define  PCI_CAP_ID_DBG		0x0A	/* Debug port */#define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */#define  PCI_CAP_ID_HOTPLUG	0x0C	/* PCI hot-plug */#define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */#define  PCI_CAP_ID_AGP3	0x0E	/* AGP 8x */#define  PCI_CAP_ID_SECURE	0x0F	/* Secure device (?) */#define  PCI_CAP_ID_EXP		0x10	/* PCI Express */#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */#define  PCI_CAP_ID_SATA	0x12	/* Serial-ATA HBA */#define  PCI_CAP_ID_AF		0x13	/* Advanced features of PCI devices integrated in PCIe root cplx */#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */#define PCI_CAP_SIZEOF		4/* Capabilities residing in the PCI Express extended configuration space */#define PCI_EXT_CAP_ID_AER	0x01	/* Advanced Error Reporting */#define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel */#define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */#define PCI_EXT_CAP_ID_PB	0x04	/* Power Budgeting */#define PCI_EXT_CAP_ID_RCLINK	0x05	/* Root Complex Link Declaration */#define PCI_EXT_CAP_ID_RCILINK	0x06	/* Root Complex Internal Link Declaration */#define PCI_EXT_CAP_ID_RCECOLL	0x07	/* Root Complex Event Collector */#define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function Virtual Channel */#define PCI_EXT_CAP_ID_RBCB	0x0a	/* Root Bridge Control Block */#define PCI_EXT_CAP_ID_VNDR	0x0b	/* Vendor specific */#define PCI_EXT_CAP_ID_ACS	0x0d	/* Access Controls *//* Power Management Registers */#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version (2=PM1.1) */#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* Clock required for PME generation */#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization required */#define  PCI_PM_CAP_AUX_C_MASK	0x01c0	/* Maximum aux current required in D3cold */#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */#define  PCI_PM_CAP_PME_D0	0x0800	/* PME can be asserted from D0 */#define  PCI_PM_CAP_PME_D1	0x1000	/* PME can be asserted from D1 */#define  PCI_PM_CAP_PME_D2	0x2000	/* PME can be asserted from D2 */#define  PCI_PM_CAP_PME_D3_HOT	0x4000	/* PME can be asserted from D3hot */#define  PCI_PM_CAP_PME_D3_COLD	0x8000	/* PME can be asserted from D3cold */#define PCI_PM_CTRL		4	/* PM control and status register */#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* PM table data index */#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* PM table data scaling factor */#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions */#define  PCI_PM_PPB_B2_B3	0x40	/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */#define  PCI_PM_BPCC_ENABLE	0x80	/* Secondary bus is power managed */#define PCI_PM_DATA_REGISTER	7	/* PM table contents read here */#define PCI_PM_SIZEOF		8/* AGP registers */#define PCI_AGP_VERSION		2	/* BCD version number */#define PCI_AGP_RFU		3	/* Rest of capability flags */#define PCI_AGP_STATUS		4	/* Status register */#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */#define  PCI_AGP_STATUS_ISOCH	0x10000	/* Isochronous transactions supported */#define  PCI_AGP_STATUS_ARQSZ_MASK	0xe000	/* log2(optimum async req size in bytes) - 4 */#define  PCI_AGP_STATUS_CAL_MASK	0x1c00	/* Calibration cycle timing */#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */#define  PCI_AGP_STATUS_ITA_COH	0x0100	/* In-aperture accesses always coherent */#define  PCI_AGP_STATUS_GART64	0x0080	/* 64-bit GART entries supported */#define  PCI_AGP_STATUS_HTRANS	0x0040	/* If 0, core logic can xlate host CPU accesses thru aperture */#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing cycles supported */