?? header.h
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#define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */#define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */#define PCI_AGP_COMMAND 8 /* Control register */#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */#define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */#define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */#define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */#define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */#define PCI_AGP_SIZEOF 12/* Slot Identification */#define PCI_SID_ESR 2 /* Expansion Slot Register */#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */#define PCI_SID_CHASSIS_NR 3 /* Chassis Number *//* Message Signalled Interrupts registers */#define PCI_MSI_FLAGS 2 /* Various flags */#define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */#define PCI_MSI_FLAGS_64BIT 0x080 /* 64-bit addresses allowed */#define PCI_MSI_FLAGS_QSIZE 0x070 /* Message queue size configured */#define PCI_MSI_FLAGS_QMASK 0x00e /* Maximum queue size available */#define PCI_MSI_FLAGS_ENABLE 0x001 /* MSI feature enabled */#define PCI_MSI_RFU 3 /* Rest of capability flags */#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */#define PCI_MSI_MASK_BIT_32 12 /* per-vector masking for 32-bit devices */#define PCI_MSI_MASK_BIT_64 16 /* per-vector masking for 64-bit devices */#define PCI_MSI_PENDING_32 16 /* per-vector interrupt pending for 32-bit devices */#define PCI_MSI_PENDING_64 20 /* per-vector interrupt pending for 64-bit devices *//* PCI-X */#define PCI_PCIX_COMMAND 2 /* Command register offset */#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070#define PCI_PCIX_COMMAND_RESERVED 0xf80#define PCI_PCIX_STATUS 4 /* Status register offset */#define PCI_PCIX_STATUS_FUNCTION 0x00000007#define PCI_PCIX_STATUS_DEVICE 0x000000f8#define PCI_PCIX_STATUS_BUS 0x0000ff00#define PCI_PCIX_STATUS_64BIT 0x00010000#define PCI_PCIX_STATUS_133MHZ 0x00020000#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */#define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */#define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */#define PCI_PCIX_SIZEOF 4/* PCI-X Bridges */#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000#define PCI_PCIX_BRIDGE_SIZEOF 12/* HyperTransport (as of spec rev. 2.00) */#define PCI_HT_CMD 2 /* Command Register */#define PCI_HT_CMD_TYP_HI 0xe000 /* Capability Type high part */#define PCI_HT_CMD_TYP_HI_PRI 0x0000 /* Slave or Primary Interface */#define PCI_HT_CMD_TYP_HI_SEC 0x2000 /* Host or Secondary Interface */#define PCI_HT_CMD_TYP 0xf800 /* Capability Type */#define PCI_HT_CMD_TYP_SW 0x4000 /* Switch */#define PCI_HT_CMD_TYP_IDC 0x8000 /* Interrupt Discovery and Configuration */#define PCI_HT_CMD_TYP_RID 0x8800 /* Revision ID */#define PCI_HT_CMD_TYP_UIDC 0x9000 /* UnitID Clumping */#define PCI_HT_CMD_TYP_ECSA 0x9800 /* Extended Configuration Space Access */#define PCI_HT_CMD_TYP_AM 0xa000 /* Address Mapping */#define PCI_HT_CMD_TYP_MSIM 0xa800 /* MSI Mapping */#define PCI_HT_CMD_TYP_DR 0xb000 /* DirectRoute */#define PCI_HT_CMD_TYP_VCS 0xb800 /* VCSet */#define PCI_HT_CMD_TYP_RM 0xc000 /* Retry Mode */#define PCI_HT_CMD_TYP_X86 0xc800 /* X86 (reserved) */ /* Link Control Register */#define PCI_HT_LCTR_CFLE 0x0002 /* CRC Flood Enable */#define PCI_HT_LCTR_CST 0x0004 /* CRC Start Test */#define PCI_HT_LCTR_CFE 0x0008 /* CRC Force Error */#define PCI_HT_LCTR_LKFAIL 0x0010 /* Link Failure */#define PCI_HT_LCTR_INIT 0x0020 /* Initialization Complete */#define PCI_HT_LCTR_EOC 0x0040 /* End of Chain */#define PCI_HT_LCTR_TXO 0x0080 /* Transmitter Off */#define PCI_HT_LCTR_CRCERR 0x0f00 /* CRC Error */#define PCI_HT_LCTR_ISOCEN 0x1000 /* Isochronous Flow Control Enable */#define PCI_HT_LCTR_LSEN 0x2000 /* LDTSTOP# Tristate Enable */#define PCI_HT_LCTR_EXTCTL 0x4000 /* Extended CTL Time */#define PCI_HT_LCTR_64B 0x8000 /* 64-bit Addressing Enable */ /* Link Configuration Register */#define PCI_HT_LCNF_MLWI 0x0007 /* Max Link Width In */#define PCI_HT_LCNF_LW_8B 0x0 /* Link Width 8 bits */#define PCI_HT_LCNF_LW_16B 0x1 /* Link Width 16 bits */#define PCI_HT_LCNF_LW_32B 0x3 /* Link Width 32 bits */#define PCI_HT_LCNF_LW_2B 0x4 /* Link Width 2 bits */#define PCI_HT_LCNF_LW_4B 0x5 /* Link Width 4 bits */#define PCI_HT_LCNF_LW_NC 0x7 /* Link physically not connected */#define PCI_HT_LCNF_DFI 0x0008 /* Doubleword Flow Control In */#define PCI_HT_LCNF_MLWO 0x0070 /* Max Link Width Out */#define PCI_HT_LCNF_DFO 0x0080 /* Doubleword Flow Control Out */#define PCI_HT_LCNF_LWI 0x0700 /* Link Width In */#define PCI_HT_LCNF_DFIE 0x0800 /* Doubleword Flow Control In Enable */#define PCI_HT_LCNF_LWO 0x7000 /* Link Width Out */#define PCI_HT_LCNF_DFOE 0x8000 /* Doubleword Flow Control Out Enable */ /* Revision ID Register */#define PCI_HT_RID_MIN 0x1f /* Minor Revision */#define PCI_HT_RID_MAJ 0xe0 /* Major Revision */ /* Link Frequency/Error Register */#define PCI_HT_LFRER_FREQ 0x0f /* Transmitter Clock Frequency */#define PCI_HT_LFRER_200 0x00 /* 200MHz */#define PCI_HT_LFRER_300 0x01 /* 300MHz */#define PCI_HT_LFRER_400 0x02 /* 400MHz */#define PCI_HT_LFRER_500 0x03 /* 500MHz */#define PCI_HT_LFRER_600 0x04 /* 600MHz */#define PCI_HT_LFRER_800 0x05 /* 800MHz */#define PCI_HT_LFRER_1000 0x06 /* 1.0GHz */#define PCI_HT_LFRER_1200 0x07 /* 1.2GHz */#define PCI_HT_LFRER_1400 0x08 /* 1.4GHz */#define PCI_HT_LFRER_1600 0x09 /* 1.6GHz */#define PCI_HT_LFRER_VEND 0x0f /* Vendor-Specific */#define PCI_HT_LFRER_ERR 0xf0 /* Link Error */#define PCI_HT_LFRER_PROT 0x10 /* Protocol Error */#define PCI_HT_LFRER_OV 0x20 /* Overflow Error */#define PCI_HT_LFRER_EOC 0x40 /* End of Chain Error */#define PCI_HT_LFRER_CTLT 0x80 /* CTL Timeout */ /* Link Frequency Capability Register */#define PCI_HT_LFCAP_200 0x0001 /* 200MHz */#define PCI_HT_LFCAP_300 0x0002 /* 300MHz */#define PCI_HT_LFCAP_400 0x0004 /* 400MHz */#define PCI_HT_LFCAP_500 0x0008 /* 500MHz */#define PCI_HT_LFCAP_600 0x0010 /* 600MHz */#define PCI_HT_LFCAP_800 0x0020 /* 800MHz */#define PCI_HT_LFCAP_1000 0x0040 /* 1.0GHz */#define PCI_HT_LFCAP_1200 0x0080 /* 1.2GHz */#define PCI_HT_LFCAP_1400 0x0100 /* 1.4GHz */#define PCI_HT_LFCAP_1600 0x0200 /* 1.6GHz */#define PCI_HT_LFCAP_VEND 0x8000 /* Vendor-Specific */ /* Feature Register */#define PCI_HT_FTR_ISOCFC 0x0001 /* Isochronous Flow Control Mode */#define PCI_HT_FTR_LDTSTOP 0x0002 /* LDTSTOP# Supported */#define PCI_HT_FTR_CRCTM 0x0004 /* CRC Test Mode */#define PCI_HT_FTR_ECTLT 0x0008 /* Extended CTL Time Required */#define PCI_HT_FTR_64BA 0x0010 /* 64-bit Addressing */#define PCI_HT_FTR_UIDRD 0x0020 /* UnitID Reorder Disable */ /* Error Handling Register */#define PCI_HT_EH_PFLE 0x0001 /* Protocol Error Flood Enable */#define PCI_HT_EH_OFLE 0x0002 /* Overflow Error Flood Enable */#define PCI_HT_EH_PFE 0x0004 /* Protocol Error Fatal Enable */#define PCI_HT_EH_OFE 0x0008 /* Overflow Error Fatal Enable */#define PCI_HT_EH_EOCFE 0x0010 /* End of Chain Error Fatal Enable */#define PCI_HT_EH_RFE 0x0020 /* Response Error Fatal Enable */#define PCI_HT_EH_CRCFE 0x0040 /* CRC Error Fatal Enable */#define PCI_HT_EH_SERRFE 0x0080 /* System Error Fatal Enable (B */#define PCI_HT_EH_CF 0x0100 /* Chain Fail */#define PCI_HT_EH_RE 0x0200 /* Response Error */#define PCI_HT_EH_PNFE 0x0400 /* Protocol Error Nonfatal Enable */#define PCI_HT_EH_ONFE 0x0800 /* Overflow Error Nonfatal Enable */#define PCI_HT_EH_EOCNFE 0x1000 /* End of Chain Error Nonfatal Enable */#define PCI_HT_EH_RNFE 0x2000 /* Response Error Nonfatal Enable */#define PCI_HT_EH_CRCNFE 0x4000 /* CRC Error Nonfatal Enable */#define PCI_HT_EH_SERRNFE 0x8000 /* System Error Nonfatal Enable *//* HyperTransport: Slave or Primary Interface */#define PCI_HT_PRI_CMD 2 /* Command Register */#define PCI_HT_PRI_CMD_BUID 0x001f /* Base UnitID */#define PCI_HT_PRI_CMD_UC 0x03e0 /* Unit Count */#define PCI_HT_PRI_CMD_MH 0x0400 /* Master Host */#define PCI_HT_PRI_CMD_DD 0x0800 /* Default Direction */#define PCI_HT_PRI_CMD_DUL 0x1000 /* Drop on Uninitialized Link */#define PCI_HT_PRI_LCTR0 4 /* Link Control 0 Register */#define PCI_HT_PRI_LCNF0 6 /* Link Config 0 Register */#define PCI_HT_PRI_LCTR1 8 /* Link Control 1 Register */#define PCI_HT_PRI_LCNF1 10 /* Link Config 1 Register */#define PCI_HT_PRI_RID 12 /* Revision ID Register */#define PCI_HT_PRI_LFRER0 13 /* Link Frequency/Error 0 Register */#define PCI_HT_PRI_LFCAP0 14 /* Link Frequency Capability 0 Register */#define PCI_HT_PRI_FTR 16 /* Feature Register */#define PCI_HT_PRI_LFRER1 17 /* Link Frequency/Error 1 Register */#define PCI_HT_PRI_LFCAP1 18 /* Link Frequency Capability 1 Register */#define PCI_HT_PRI_ES 20 /* Enumeration Scratchpad Register */#define PCI_HT_PRI_EH 22 /* Error Handling Register */#define PCI_HT_PRI_MBU 24 /* Memory Base Upper Register */#define PCI_HT_PRI_MLU 25 /* Memory Limit Upper Register */#define PCI_HT_PRI_BN 26 /* Bus Number Register */#define PCI_HT_PRI_SIZEOF 28/* HyperTransport: Host or Secondary Interface */#define PCI_HT_SEC_CMD 2 /* Command Register */#define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */#define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */#define PCI_HT_SEC_CMD_DN 0x0076 /* Device Number */#define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */#define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */#define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */#define PCI_HT_SEC_CMD_HIECE 0x0800 /* Host Inbound End of Chain Error */#define PCI_HT_SEC_CMD_DUL 0x1000 /* Drop on Uninitialized Link */#define PCI_HT_SEC_LCTR 4 /* Link Control Register */#define PCI_HT_SEC_LCNF 6 /* Link Config Register */#define PCI_HT_SEC_RID 8 /* Revision ID Register */#define PCI_HT_SEC_LFRER 9 /* Link Frequency/Error Register */#define PCI_HT_SEC_LFCAP 10 /* Link Frequency Capability Register */#define PCI_HT_SEC_FTR 12 /* Feature Register */#define PCI_HT_SEC_FTR_EXTRS 0x0100 /* Extended Register Set */#define PCI_HT_SEC_FTR_UCNFE 0x0200 /* Upstream Configuration Enable */#define PCI_HT_SEC_ES 16 /* Enumeration Scratchpad Register */#define PCI_HT_SEC_EH 18 /* Error Handling Register */#define PCI_HT_SEC_MBU 20 /* Memory Base Upper Register */#define PCI_HT_SEC_MLU 21 /* Memory Limit Upper Register */#define PCI_HT_SEC_SIZEOF 24/* HyperTransport: Switch */#define PCI_HT_SW_CMD 2 /* Switch Command Register */#define PCI_HT_SW_CMD_VIBERR 0x0080 /* VIB Error */#define PCI_HT_SW_CMD_VIBFL 0x0100 /* VIB Flood */#define PCI_HT_SW_CMD_VIBFT 0x0200 /* VIB Fatal */#define PCI_HT_SW_CMD_VIBNFT 0x0400 /* VIB Nonfatal */?? 快捷鍵說(shuō)明
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