#define  PCI_EXP_SLTCAP_MRL	0x0004	/* MRL Sensor Present */#define  PCI_EXP_SLTCAP_ATNI	0x0008	/* Attention Indicator Present */#define  PCI_EXP_SLTCAP_PWRI	0x0010	/* Power Indicator Present */#define  PCI_EXP_SLTCAP_HPS	0x0020	/* Hot-Plug Surprise */#define  PCI_EXP_SLTCAP_HPC	0x0040	/* Hot-Plug Capable */#define  PCI_EXP_SLTCAP_PWR_VAL	0x00007f80 /* Slot Power Limit Value */#define  PCI_EXP_SLTCAP_PWR_SCL	0x00018000 /* Slot Power Limit Scale */#define  PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */#define  PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */#define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */#define PCI_EXP_SLTCTL		0x18	/* Slot Control */#define  PCI_EXP_SLTCTL_ATNB	0x0001	/* Attention Button Pressed Enable */#define  PCI_EXP_SLTCTL_PWRF	0x0002	/* Power Fault Detected Enable */#define  PCI_EXP_SLTCTL_MRLS	0x0004	/* MRL Sensor Changed Enable */#define  PCI_EXP_SLTCTL_PRSD	0x0008	/* Presence Detect Changed Enable */#define  PCI_EXP_SLTCTL_CMDC	0x0010	/* Command Completed Interrupt Enable */#define  PCI_EXP_SLTCTL_HPIE	0x0020	/* Hot-Plug Interrupt Enable */#define  PCI_EXP_SLTCTL_ATNI	0x00c0	/* Attention Indicator Control */#define  PCI_EXP_SLTCTL_PWRI	0x0300	/* Power Indicator Control */#define  PCI_EXP_SLTCTL_PWRC	0x0400	/* Power Controller Control */#define  PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */#define  PCI_EXP_SLTCTL_LLCHG	0x1000	/* Data Link Layer State Changed Enable */#define PCI_EXP_SLTSTA		0x1a	/* Slot Status */#define  PCI_EXP_SLTSTA_ATNB	0x0001	/* Attention Button Pressed */#define  PCI_EXP_SLTSTA_PWRF	0x0002	/* Power Fault Detected */#define  PCI_EXP_SLTSTA_MRLS	0x0004	/* MRL Sensor Changed */#define  PCI_EXP_SLTSTA_PRSD	0x0008	/* Presence Detect Changed */#define  PCI_EXP_SLTSTA_CMDC	0x0010	/* Command Completed */#define  PCI_EXP_SLTSTA_MRL_ST	0x0020	/* MRL Sensor State */#define  PCI_EXP_SLTSTA_PRES	0x0040	/* Presence Detect State */#define  PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */#define  PCI_EXP_SLTSTA_LLCHG	0x0100	/* Data Link Layer State Changed */#define PCI_EXP_RTCTL		0x1c	/* Root Control */#define  PCI_EXP_RTCTL_SECEE	0x0001	/* System Error on Correctable Error */#define  PCI_EXP_RTCTL_SENFEE	0x0002	/* System Error on Non-Fatal Error */#define  PCI_EXP_RTCTL_SEFEE	0x0004	/* System Error on Fatal Error */#define  PCI_EXP_RTCTL_PMEIE	0x0008	/* PME Interrupt Enable */#define  PCI_EXP_RTCTL_CRSVIS	0x0010	/* Configuration Request Retry Status Visible to SW */#define PCI_EXP_RTCAP		0x1e	/* Root Capabilities */#define  PCI_EXP_RTCAP_CRSVIS	0x0010	/* Configuration Request Retry Status Visible to SW */#define PCI_EXP_RTSTA		0x20	/* Root Status */#define  PCI_EXP_RTSTA_PME_REQID   0x0000ffff /* PME Requester ID */#define  PCI_EXP_RTSTA_PME_STATUS  0x00010000 /* PME Status */#define  PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending *//* MSI-X */#define  PCI_MSIX_ENABLE	0x8000#define  PCI_MSIX_MASK		0x4000#define  PCI_MSIX_TABSIZE	0x03ff#define PCI_MSIX_TABLE		4#define PCI_MSIX_PBA		8#define  PCI_MSIX_BIR		0x7/* Subsystem vendor/device ID for PCI bridges */#define PCI_SSVID_VENDOR	4#define PCI_SSVID_DEVICE	6/* Advanced Error Reporting */#define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */#define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */#define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */#define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */#define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */#define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */#define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */#define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */#define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */#define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */#define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */#define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */#define PCI_ERR_UNCOR_MASK	8	/* Uncorrectable Error Mask */	/* Same bits as above */#define PCI_ERR_UNCOR_SEVER	12	/* Uncorrectable Error Severity */	/* Same bits as above */#define PCI_ERR_COR_STATUS	16	/* Correctable Error Status */#define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */#define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */#define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */#define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */#define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */#define PCI_ERR_COR_MASK	20	/* Correctable Error Mask */	/* Same bits as above */#define PCI_ERR_CAP		24	/* Advanced Error Capabilities */#define  PCI_ERR_CAP_FEP(x)	((x) & 31)	/* First Error Pointer */#define  PCI_ERR_CAP_ECRC_GENC	0x00000020	/* ECRC Generation Capable */#define  PCI_ERR_CAP_ECRC_GENE	0x00000040	/* ECRC Generation Enable */#define  PCI_ERR_CAP_ECRC_CHKC	0x00000080	/* ECRC Check Capable */#define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */#define PCI_ERR_HEADER_LOG	28	/* Header Log Register (16 bytes) */#define PCI_ERR_ROOT_COMMAND	44	/* Root Error Command */#define PCI_ERR_ROOT_STATUS	48#define PCI_ERR_ROOT_COR_SRC	52#define PCI_ERR_ROOT_SRC	54/* Virtual Channel */#define PCI_VC_PORT_REG1	4#define PCI_VC_PORT_REG2	8#define PCI_VC_PORT_CTRL	12#define PCI_VC_PORT_STATUS	14#define PCI_VC_RES_CAP		16#define PCI_VC_RES_CTRL		20#define PCI_VC_RES_STATUS	26/* Power Budgeting */#define PCI_PWR_DSR		4	/* Data Select Register */#define PCI_PWR_DATA		8	/* Data Register */#define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */#define  PCI_PWR_DATA_SCALE(x)	(((x) >> 8) & 3)    /* Data Scale */#define  PCI_PWR_DATA_PM_SUB(x)	(((x) >> 10) & 7)   /* PM Sub State */#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */#define  PCI_PWR_DATA_TYPE(x)	(((x) >> 15) & 7)   /* Type */#define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */#define PCI_PWR_CAP		12	/* Capability */#define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget *//* * The PCI interface treats multi-function devices as independent * devices.  The slot/function address of each device is encoded * in a single byte as follows: * *	7:3 = slot *	2:0 = function */#define PCI_DEVFN(slot,func)	((((slot) & 0x1f) << 3) | ((func) & 0x07))#define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)#define PCI_FUNC(devfn)		((devfn) & 0x07)/* Device classes and subclasses */#define PCI_CLASS_NOT_DEFINED		0x0000#define PCI_CLASS_NOT_DEFINED_VGA	0x0001#define PCI_BASE_CLASS_STORAGE		0x01#define PCI_CLASS_STORAGE_SCSI		0x0100#define PCI_CLASS_STORAGE_IDE		0x0101#define PCI_CLASS_STORAGE_FLOPPY	0x0102#define PCI_CLASS_STORAGE_IPI		0x0103#define PCI_CLASS_STORAGE_RAID		0x0104#define PCI_CLASS_STORAGE_ATA		0x0105#define PCI_CLASS_STORAGE_SATA		0x0106#define PCI_CLASS_STORAGE_SAS		0x0107#define PCI_CLASS_STORAGE_OTHER		0x0180#define PCI_BASE_CLASS_NETWORK		0x02#define PCI_CLASS_NETWORK_ETHERNET	0x0200#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201#define PCI_CLASS_NETWORK_FDDI		0x0202#define PCI_CLASS_NETWORK_ATM		0x0203#define PCI_CLASS_NETWORK_ISDN		0x0204#define PCI_CLASS_NETWORK_OTHER		0x0280#define PCI_BASE_CLASS_DISPLAY		0x03#define PCI_CLASS_DISPLAY_VGA		0x0300#define PCI_CLASS_DISPLAY_XGA		0x0301#define PCI_CLASS_DISPLAY_3D		0x0302#define PCI_CLASS_DISPLAY_OTHER		0x0380#define PCI_BASE_CLASS_MULTIMEDIA	0x04#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402#define PCI_CLASS_MULTIMEDIA_AUDIO_DEV	0x0403#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480#define PCI_BASE_CLASS_MEMORY		0x05#define  PCI_CLASS_MEMORY_RAM		0x0500#define  PCI_CLASS_MEMORY_FLASH		0x0501#define  PCI_CLASS_MEMORY_OTHER		0x0580#define PCI_BASE_CLASS_BRIDGE		0x06#define  PCI_CLASS_BRIDGE_HOST		0x0600#define  PCI_CLASS_BRIDGE_ISA		0x0601#define  PCI_CLASS_BRIDGE_EISA		0x0602#define  PCI_CLASS_BRIDGE_MC		0x0603#define  PCI_CLASS_BRIDGE_PCI		0x0604#define  PCI_CLASS_BRIDGE_PCMCIA	0x0605#define  PCI_CLASS_BRIDGE_NUBUS		0x0606#define  PCI_CLASS_BRIDGE_CARDBUS	0x0607#define  PCI_CLASS_BRIDGE_RACEWAY	0x0608#define  PCI_CLASS_BRIDGE_PCI_SEMI	0x0609#define  PCI_CLASS_BRIDGE_IB_TO_PCI	0x060a#define  PCI_CLASS_BRIDGE_OTHER		0x0680#define PCI_BASE_CLASS_COMMUNICATION	0x07#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701#define PCI_CLASS_COMMUNICATION_MSERIAL	0x0702#define PCI_CLASS_COMMUNICATION_MODEM	0x0703#define PCI_CLASS_COMMUNICATION_OTHER	0x0780#define PCI_BASE_CLASS_SYSTEM		0x08#define PCI_CLASS_SYSTEM_PIC		0x0800#define PCI_CLASS_SYSTEM_DMA		0x0801#define PCI_CLASS_SYSTEM_TIMER		0x0802#define PCI_CLASS_SYSTEM_RTC		0x0803#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804#define PCI_CLASS_SYSTEM_OTHER		0x0880#define PCI_BASE_CLASS_INPUT		0x09#define PCI_CLASS_INPUT_KEYBOARD	0x0900#define PCI_CLASS_INPUT_PEN		0x0901#define PCI_CLASS_INPUT_MOUSE		0x0902#define PCI_CLASS_INPUT_SCANNER		0x0903#define PCI_CLASS_INPUT_GAMEPORT	0x0904#define PCI_CLASS_INPUT_OTHER		0x0980#define PCI_BASE_CLASS_DOCKING		0x0a#define PCI_CLASS_DOCKING_GENERIC	0x0a00#define PCI_CLASS_DOCKING_OTHER		0x0a80#define PCI_BASE_CLASS_PROCESSOR	0x0b#define PCI_CLASS_PROCESSOR_386		0x0b00#define PCI_CLASS_PROCESSOR_486		0x0b01#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20#define PCI_CLASS_PROCESSOR_MIPS	0x0b30#define PCI_CLASS_PROCESSOR_CO		0x0b40#define PCI_BASE_CLASS_SERIAL		0x0c#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00#define PCI_CLASS_SERIAL_ACCESS		0x0c01#define PCI_CLASS_SERIAL_SSA		0x0c02#define PCI_CLASS_SERIAL_USB		0x0c03#define PCI_CLASS_SERIAL_FIBER		0x0c04#define PCI_CLASS_SERIAL_SMBUS		0x0c05#define PCI_CLASS_SERIAL_INFINIBAND	0x0c06#define PCI_BASE_CLASS_WIRELESS		0x0d#define PCI_CLASS_WIRELESS_IRDA		0x0d00#define PCI_CLASS_WIRELESS_CONSUMER_IR	0x0d01#define PCI_CLASS_WIRELESS_RF		0x0d10#define PCI_CLASS_WIRELESS_OTHER	0x0d80#define PCI_BASE_CLASS_INTELLIGENT	0x0e#define PCI_CLASS_INTELLIGENT_I2O	0x0e00#define PCI_BASE_CLASS_SATELLITE	0x0f#define PCI_CLASS_SATELLITE_TV		0x0f00#define PCI_CLASS_SATELLITE_AUDIO	0x0f01#define PCI_CLASS_SATELLITE_VOICE	0x0f03#define PCI_CLASS_SATELLITE_DATA	0x0f04#define PCI_BASE_CLASS_CRYPT		0x10#define PCI_CLASS_CRYPT_NETWORK		0x1000#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1010#define PCI_CLASS_CRYPT_OTHER		0x1080#define PCI_BASE_CLASS_SIGNAL		0x11#define PCI_CLASS_SIGNAL_DPIO		0x1100#define PCI_CLASS_SIGNAL_PERF_CTR	0x1101#define PCI_CLASS_SIGNAL_SYNCHRONIZER	0x1110#define PCI_CLASS_SIGNAL_OTHER		0x1180#define PCI_CLASS_OTHERS		0xff/* Several ID's we need in the library */#define PCI_VENDOR_ID_INTEL		0x8086#define PCI_VENDOR_ID_COMPAQ		0x0e11