//! @file psc_drv.h,v
//!
//! Copyright (c) 2004 Atmel.
//!
//! Please read file license.txt for copyright notice.
//!
//! @brief This file contains the low level macros and definition for the PSC use
//!
//! @version 1.5 at90pwm3-lib-mcu-0_0_2
//!
//! @todo
//! @bug

#ifndef PSC_DRV_H
#define PSC_DRV_H

//_____  I N C L U D E S ___________________________________________________
#include "lib_mcu/pll/pll_drv.h"

//! @defgroup PSC_modules PSC Modules
//! PSC Modules
//! @{

//_____ M A C R O S ________________________________________________________

   //! @defgroup PSC0_macros PSC0 Macros
   //! PSC0 Macros
   //! @{

      //! @defgroup PSC0_output_configuration PSC0 Output Configuration
      //! Select the PSC0 Outputs
      //! @{
#define Enable_pscout00()                             (PSOC0 |=  (1<<POEN0A) )  //!< Enable PSC0 Waveform Generator A
#define Disable_pscout00()                            (PSOC0 &= ~(1<<POEN0A) )  //!< Disable PSC0 Waveform Generator A

#define Enable_pscout01()                             (PSOC0 |=  (1<<POEN0B) )  //!< Enable PSC0 Waveform Generator B
#define Disable_pscout01()                            (PSOC0 &= ~(1<<POEN0B) )  //!< Disable PSC0 Waveform Generator B
//! Enable Both PSC0 Waveform Generator A and B
#define Enable_both_psc0_outputs()                                            \
           (PSOC0 |=  ((1<<POEN0A) | (1<<POEN0B)))
//! Disable Both PSC0 Waveform Generator A and B
#define Disable_both_psc0_outputs()                                           \
           (PSOC0 &= ~((1<<POEN0A) | (1<<POEN0B)))

#define Psc0_outputs_active_high()                    (PCNF0 |=  (1<<POP0) )    //!< PSC0 outputs are active low
#define Psc0_outputs_active_low()                     (PCNF0 &= ~(1<<POP0) )    //!< PSC0 outputs are active high
      //! @}

      //! @defgroup SPC0_mode_control_module PSC0 Mode Control
      //! PSC0C Mode ontrol
      //! @{
#define Enable_psc0_fifty_percent_mode()              (PCNF0 |=  (1<<PFIFTY0) )  //!< PSC0 is in 50% mode: Only OCR0RBH/L and OCR0SBH/L are used. They are duplicated in OCR0R/SAH/L during the update of OCR0BH/L
#define Disable_psc0_fifty_percent_mode()             (PCNF0 &= ~(1<<PFIFTY0) )  //!< OCR0R/SAH/L and OCR0R/SBH/L are fully independant

#define Enable_psc0_autolock_mode()                   (PCNF0 |=  (1<<PALOCK0) )  //!< OCR0R/SAH/L and OCR0R/SBH/L can be written without disturbing the PSC cycle. The update of these registers will be proceed at the end of the PSC cycle if the OCR0RB has been last written
#define Disable_psc0_autolock_mode()                  (PCNF0 &= ~(1<<PALOCK0) )  //!< The update will be procced according to PLOCK0 bit

#define Lock_psc0_compare_values()                    (PCNF0 |=  (1<<PLOCK0) )   //!< Take care that the lock is active only if you have disabled the autolock mode
#define Update_psc0_compare_values()                  (PCNF0 &= ~(1<<PLOCK0) )   //!< The compare registers will be updated with the content of OCR0ARH/L and OCR0BRH
      //! @}

      //! @defgroup PSC0_clock_control PSC0 Clock Control
      //! PSC0 Clock Control
      //! @{

         //! @defgroup PSC0_clock_selection PSC0 Clock Selection
         //! PSC0 Clock Selection
         //! @{
//! Connect the PSC0 input clock to the PLL
#define Psc0_use_pll_clock()                          (PCNF0 |= (1<<PCLKSEL0) )
//! Connect the PSC0 input clock to the I/O clock
#define Psc0_use_io_clock()                           (PCNF0 &= ~(1<<PCLKSEL0) )
//! Start the PLL at 64MHz and connect it to PSC0
#define Psc0_use_64_mega_pll_clock()                                          \
          (Start_pll_64_mega();                                               \
           Wait_pll_ready(),\
           Psc0_use_pll_clock() )
//! Start the PLL at 32MHz and connect it to PSC0
#define Psc0_use_32_mega_pll_clock()                                          \
          (Start_pll_32_mega(),                                               \
           Wait_pll_ready(),                                                  \
           Psc0_use_pll_clock() )
         //! @}

         //! @defgroup PSC0_prescaler_control PSC0 Prescaler Control
         //! PSC0 Prescaler Control
         //! @{
//! No PSC0prescaler
#define Disable_psc0_prescaler()                                              \
           (PCTL0 &= ~(  (1<<PPRE01) | (1<<PPRE00) ) )
//! PSC0 clock is internally divided by 4
#define Divide_psc0_input_clock_by_4()                                        \
           (PCTL0 &= ~(1<<PPRE01),                                            \
            PCTL0 |=  (1<<PPRE00) )
//! PSC0 clock is internally divided by 16
#define Divide_psc0_input_clock_by_16()                                       \
           (PCTL0 |=  (1<<PPRE01),                                            \
            PCTL0 &= ~(1<<PPRE00) )
//! PSC0 clock is internally divided by 64
#define Divide_psc0_input_clock_by_64()                                       \
           (PCTL0 |=  ((1<<PPRE01) | (1<<PPRE00)) )
         //! @}

      //! @}

      //! @defgroup PSC0_ramp_mode_selection PSC0 Ramp Mode Selection
      //! PSC0 Ramp Mode Selection
      //! @{
      //! PSC0 is configured in one ramp mode, it means that the internal counter
      //! counts from 0 up to OCR0RB
#define Psc0_in_1_ramp_mode()                                                 \
           (PCNF0 &= ~(  (1<<PMODE01) | (1<<PMODE00) ) )
//! PSC0 is configured in two ramp mode, it means that the internal counter
//! counts from 0 up to OCR0RA then from 0 to OCR0RB
#define Psc0_in_2_ramps_mode()                                                \
           (PCNF0 &= ~(1<<PMODE01),                                           \
            PCNF0 |=  (1<<PMODE00) )
//! PSC0 is configured in for ramp mode, it means that the internal counter
//! counts from 0 up to OCR0SA then from 0 to OCR0RA then from 0 to OCR0SB then from 0 to OCR0RB
#define Psc0_in_4_ramps_mode()                                                \
           (PCNF0 |=  (1<<PMODE01),                                           \
            PCNF0 &= ~(1<<PMODE00) )
//! PSC0 is configured in for ramp mode, it means that the internal counter
//! counts from 0 up to OCR0RB then from OCR0RB downto 0
#define Psc0_in_centered_aligned_mode()                                       \
           (PCNF0 |=  (  (1<<PMODE01) | (1<<PMODE00) ) )
      //! @}

      //! @defgroup PSC0_flank_width_modulation_configuration PSC0 Flank Width Modulation Configuration
      //! Select PSC0 Flank Width Modulation Configuration
      //! @{
#define Psc0_symetrical_flank_width_modulation()      (PCTL0 |=  (1<<PBFM0) )     //!< PSC0 Flank width modulation operates on both OCR0RA and OCR0RB
#define Psc0_end_of_cycle_flank_width_modulation()    (PCTL0 &= ~(1<<PBFM0) )     //!< PSC0 Flank width modulation operates only on OCR0RB
      //! @}

      //! @defgroup PSC0_adc_amplifier_trigger_configuration PSC0 ADC Amplifier Trigger Configuration
      //! Select the PSC0 trigger configuration for the ADC or the amplifier
      //! @{
//! The PSC0 synchronization signal is sent to the ADC/Amplifier on waveform generator A leading edge
#define Psc0_synchro_on_waveform_generator_a_leading_edge()                   \
           (PSCO0 &= ~(  (1<<PSYNC01) | (1<<PSYNC00) ) )
//! The PSC0 synchronization signal is sent to the ADC/Amplifier on waveform generator A trailing edge
#define Psc0_synchro_on_waveform_generator_a_trailing_edge()                  \
           (PSCO0 &= ~(1<<PSYNC01),                                           \
            PSCO0 |=  (1<<PSYNC00) )
//! The PSC0 synchronization signal is sent to the ADC/Amplifier on waveform generator B leading edge
#define Psc0_synchro_on_waveform_generator_b_leading_edge()                   \
           (PSCO0 |=  (1<<PSYNC01),                                           \
            PSCO0 &= ~(1<<PSYNC00) )
//! The PSC0 synchronization signal is sent to the ADC/Amplifier on waveform generator B trailing edge
#define Psc0_synchro_on_waveform_generator_b_trailing_edge()                  \
           (PSCO0 |=  (  (1<<PSYNC01) | (1<<PSYNC00) ) )
      //! @}

      //! @defgroup PSC0_run_control PSC0 Run Control
      //! Turn On and Off the PSC0
      //! @{
#define Start_psc0()                                  (PCTL0 |=  (1<<PRUN0) )     //!< Turn On PSC0
#define Stop_psc0()                                   (PCTL0 &= ~(1<<PRUN0) )     //!< Turn Off PSC0
//! Turn Off PSC0 and the end of cycle
#define Psc0_complete_waveform_and_stop()             (PCTL0 |=  (1<<PCCYC0), \
                                                       PCTL0 &= ~(1<<PRUN0) )
#define Is_psc0_started()                             (PCTL0 & (1<<PRUN0) )
      //! @}

      //! @defgroup PSC0_fault_mode_configuration PSC0 Fault Mode Configuration
      //! PSC0 Fault Mode Configuration
      //! @{
#define Enable_pscout00_fault_mode()                  (PCTL0 |=  (1<<PAOC0A) )    //!< Fault input select to block A can act directly to PSCOUT00 output
#define Disable_pscout00_fault_mode()                 (PCTL0 &= ~(1<<PAOC0A) )    //!< No fault or retrigger management on PSCOUT00

#define Enable_pscout01_fault_mode()                  (PCTL0 |=  (1<<PAOC0B) )    //!< Fault input select to block A can act directly to PSCOUT00 output
#define Disable_pscout01_fault_mode()                 (PCTL0 &= ~(1<<PAOC0B) )    //!< No fault or retrigger management on PSCOUT01

#define Enable_psc0_autorun()                         (PCTL0 |=  (1<<PARUN0) )    //!< Setting PRUN2 in PCTL2 register or setting both PARUN2 in PCTL2 register and PRUN1 in PCTL1 register will make the two PSC start simultaneously
#define Disable_psc0_autorun()                        (PCTL0 &= ~(1<<PARUN0) )    //!< No synchronization between PSC2 and PSC0 exists
      //! @}

      //! @defgroup PSC0_interrupt_configuration PSC0 Interrupt Configuration
      //! PSC0 interrupt configuration
      //! @{
#define Enable_psc0_synchro_error_interrupt()         (PIM0 |=  (1<<PSEIE0) )     //!< An interrupt is generated when the PSEI0 bit is set
#define Disable_psc0_synchro_error_interrupt()        (PIM0 &= ~(1<<PSEIE0) )     //!< No interrupt is generated when the PSEI0 bit is set

#define Enable_psc0_external_event_a_interrupt()      (PIM0 |=  (1<<PEVE0A) )     //!< An external event which can generate a capture from retrigger/fault block A generates an interrupt
#define Disable_psc0_external_event_a_interrupt()     (PIM0 &= ~(1<<PEVE0A) )     //!< An external event which can generate a capture from retrigger/fault block A doesn't generate any interrupt

#define Enable_psc0_external_event_b_interrupt()      (PIM0 |=  (1<<PEVE0B) )     //!< An external event which can generate a capture from retrigger/fault block B generates an interrupt
#define Disable_psc0_external_event_b_interrupt()     (PIM0 &= ~(1<<PEVE0B) )     //!< An external event which can generate a capture from retrigger/fault block B doesn't generate any interrupt

#define Enable_psc0_end_of_cycle_interrupt()          (PIM0 |=  (1<<PEOPE0) )     //!< An interrupt is generated when PSC0 reaches the end of the whole cycle
#define Disable_psc0_end_of_cycle_interrupt()         (PIM0 &= ~(1<<PEOPE0) )     //!< No interrupt is generated when PSC0 reaches the end of the whole cycle
      //! @}

      //! @defgroup PSC0_interrupt_flag_control PSC0 Interrupt Flag Control
      //! PSC0 interrupt flag control
      //! @{
#define Is_psc0_synchro_error_interrupt_flag_set()    (PIFR0 & (1<<PSEI0) )       //!< Return 1 if the PSEI0 bit in PIFR0 is set
#define Clear_psc0_synchro_error_interrupt_flag()     (PIFR0 &= ~(1<<PSEI0) )     //!< Clear PSEI0 bit in PIFR0 register

#define Is_psc0_external_event_a_interrupt_flag_set() (PIFR0 & (1<<PEV0A) )       //!< Return 1 if the PEV0A bit in PIFR0 is set
#define Clear_psc0_external_event_a_interrupt_flag()  (PIFR0 &= ~(1<<PEV0A) )     //!< Clear PEV0A bit in PIFR0 register

#define Is_psc0_external_event_b_interrupt_flag_set() (PIFR0 & (1<<PEV0B) )       //!< Return 1 if the PEV0B bit in PIFR0 is set
#define Clear_psc0_external_event_b_interrupt_flag()  (PIFR0 &= ~(1<<PEV0B) )     //!< Clear PEV0B bit in PIFR0 register

#define Is_psc0_end_of_cycle_interrupt_flag_set()     (PIFR0 & (1<<PEOP2) )       //!< Return 1 if the PE0P2 bit in PIFR0 is set
#define Clear_psc0_end_of_cycle_interrupt_flag()           (PIFR0 &= ~(1<<PEOP2) )     //!< Clear PEOP2 bit in PIFR0 register
      //! @}

      //! @defgroup PSC0_comparison_value_initilization PSC0 Comparison Value Initialization
      //! This section allows to fully initilaize the comprison values
      //! @{
//! Init all PSC0 comparison values
#define Init_psc0_all_compare_values(PSC0_DEADTIME0, PSC0_ONTIME0, PSC0_DEADTIME1, PSC0_ONTIME1)  \
           (OCR0SAH = HIGH((U16)PSC0_DEADTIME0),                              \
            OCR0SAL = LOW ((U16)PSC0_DEADTIME0),                              \
            OCR0RAH = HIGH((U16)PSC0_ONTIME0),                                \
            OCR0RAL = LOW ((U16)PSC0_ONTIME0),                                \
            OCR0SBH = HIGH((U16)PSC0_DEADTIME1),                              \
            OCR0SBL = LOW ((U16)PSC0_DEADTIME1),                              \
            OCR0RBH = HIGH((U16)PSC0_ONTIME1),                                \
            OCR0RBL = LOW ((U16)PSC0_ONTIME1)   )
//! Init PSC0 fifty percent comparison values (usefull for 50% mode)
#define Init_psc0_fifty_percent_compare_values(PSC0_DEADTIME1, PSC0_ONTIME1)              \
           (OCR0SBH = HIGH((U16)PSC0_DEADTIME1),                              \
            OCR0SBL = LOW ((U16)PSC0_DEADTIME1),                              \
            OCR0RBH = HIGH((U16)PSC0_ONTIME1),                                \
            OCR0RBL = LOW ((U16)PSC0_ONTIME1)   )
      //! @}

   //! @}


   //! @defgroup PSC1_macros PSC1 Macros
   //! PSC1 Macros
   //! @{

      //! @defgroup PSC1_output_configuration PSC1 Output Configuration
      //! Select the PSC1 Outputs
      //! @{
#define Enable_pscout10()                             (PSOC1 |=  (1<<POEN1A) )  //!< Enable PSC1 Waveform Generator A