.file     "eport.s"
    .text

    .import  ISR_EPORT11                      
    
    .export  ISR_EPORT1_s                   //block entry 
    .align 4
    
ISR_EPORT1_s:
	subi	r0,28
	subi	r0,4					
	subi	r0,28					
    stm		r1-r15,(r0) 			            

	subi	r0,8					

	mfcr	r1,EPC					
	st.w    r1,(r0,0)

	mfcr	r1,EPSR					
	st.w 	r1,(r0,4)                     //site save 
	


              		
	
    lrw      r3,0x00CE0006                //EPORT Flag Register address
    movi     r2,0x00                      
    bseti    r2,0
    st.b     r2,(r3,0)                    
    
    
    
         
    
    
    lrw      r3,0x00c50001                //Mask Priority Level  0 1 2 3
    movi     r2,0x00                      
    bseti    r2,0
    bseti    r2,1
    st.b     r2,(r3,0)                    
    
    
    

    mfcr	r1,PSR				 
	bseti   r1,8
	bseti   r1,6
	mtcr 	r1,PSR                        //Enable interrupt
	 
	
	jbsr	ISR_EPORT11                   //jump Sever function
	
	
	lrw      r3,0x00c50001                //Mask Priority Level 1  ENABLE   2  3
    movi     r2,0x00                      
    bseti    r2,0
    st.b     r2,(r3,0)   
	
	

	ld.w 	r1,(r0,4)				
	mtcr	r1,EPSR

	ld.w 	r1,(r0,0)				
	mtcr	r1,EPC

	addi	r0,8					

	ldm		r1-r15,(r0)			
	addi	r0,28
	addi	r0,4					
	addi	r0,28					       //site  recovery
	rte
	
//*********************************************************
    .import  PIT1_Service
    
    .export  ISR_PIT1_S
    .align 4
    
ISR_PIT1_S:
	subi	r0,32					## Decrement SP to save registers
	subi	r0,28					## Decrement SP to save registers
	stm		r1-r15,(r0) 			## Save all registers to the stack

	subi	r0,8					## Decrement SP to save PC and PSR

	mfcr	r1,EPC					## Save the PC for the current task
	stw 	r1,(r0,0)

	mfcr	r1,EPSR					## Save the PSR for the current task
	stw 	r1,(r0,4)

	PCSR	 =0x00c80000            
	PCSR_PIF =0x2               		
	
	lrw		r1,PCSR					## Acknowledge the PIT timer interrupt
	ldw		r2,(r1)
	bseti	r2,PCSR_PIF
	stw		r2,(r1)
	
	lrw      r3,0x00c50001                //Mask Priority Level 1 
    movi     r2,0x00                      
    bseti    r2,0
    st.b     r2,(r3,0)      
	
	

	mfcr	r1,PSR					## allow interrupt is sampled 
	bseti   r1,8
	bseti   r1,6
	mtcr 	r1,PSR
	
	jbsr	PIT1_Service	
	
    lrw      r3,0x00c50001                //No Mask.
    movi     r2,0x00                      
    st.b     r2,(r3,0)     
	
	
	

	ldw 	r1,(r0,4)				## Get the PSR for the task
	mtcr	r1,EPSR

	ldw 	r1,(r0,0)				## Get the PC for the task
	mtcr	r1,EPC

	addi	r0,8					## Increment SP past the PC and PSR

	ldm		r1-r15,(r0) 			## Load all registers from the stack
	addi	r0,28					## Increment SP past the registers
	addi	r0,32					## Increment SP past the registers
	rte
	
    .import  PIT2_Service
    
    .export  ISR_PIT2_S
    .align 4
    
ISR_PIT2_S:
	subi	r0,32					## Decrement SP to save registers
	subi	r0,28					## Decrement SP to save registers
	stm		r1-r15,(r0) 			## Save all registers to the stack

	subi	r0,8					## Decrement SP to save PC and PSR

	mfcr	r1,EPC					## Save the PC for the current task
	stw 	r1,(r0,0)

	mfcr	r1,EPSR					## Save the PSR for the current task
	stw 	r1,(r0,4)
    
	PCSR	 =0x00c90000            
	PCSR_PIF =0x02               		
	PCSR_PIE =0x03
	
	lrw		r1,PCSR					## Acknowledge the PIT timer interrupt  開啟 PCSR_PIE
	ldw		r2,(r1)
	bclri   r2,PCSR_PIE
	bseti	r2,PCSR_PIF
	stw		r2,(r1)
	
	
	
    lrw      r3,0x00c50001                //Mask Priority Level  1 2
    movi     r2,0x00                      
    bseti    r2,1
    st.b     r2,(r3,0)                   
	
	
	
	
	
	
	mfcr	r1,PSR					## allow interrupt is sampled
	bseti   r1,8
	bseti   r1,6
	mtcr 	r1,PSR
	
	jbsr	PIT2_Service	
	
	
    lrw      r3,0x00c50001                //No Mask, ENABLE  1 
    movi     r2,0x00                      
    st.b     r2,(r3,0)  
    
    

	ldw 	r1,(r0,4)				## Get the PSR for the task
	mtcr	r1,EPSR

	ldw 	r1,(r0,0)				## Get the PC for the task
	mtcr	r1,EPC

	addi	r0,8					## Increment SP past the PC and PSR

	ldm		r1-r15,(r0) 			## Load all registers from the stack
	addi	r0,28					## Increment SP past the registers
	addi	r0,32					## Increment SP past the registers
	rte