?? sci264.asm
字號(hào):
st7/ ; The first line is reserved
; for specifying the instruction set
; of the targetted processor
;+------------------------------------------------------------------------------+
;| |
;| SCI COMMUNICATION BETWEEN ST7 AND PC |
;| |
;| Copyright (c), STMicroelectronics |
;| |
;+------------------------------------------------------------------------------+
;| The present source code which is for guidance only aims at providing |
;| customers with information regarding their products in order for them to save|
;| time. As a result, STMcroelectronics shall not be held liable for any direct,|
;| indirect or consequential damages with respect to any claims arising from the|
;| content of such a source code and/or the use made by customers of the |
;| information contained herein in connexion with their products. |
;+------------------------------------------------------------------------------+
;| |
;| File: sci264.asm |
;| |
;+----------------------+-----------------------+-------------------------------+
;| DATE | VERSION | HISTORY/CHANGES |
;| (MM/DD/YY) | VX.Y | |
;+----------------------+-----------------------+-------------------------------+
;| 01/17/02 | 2.0 | ST72311 ----> ST72264 |
;+----------------------+-----------------------+-------------------------------+
;|SOFTWARE DESCRIPTION: |
;| ST7 SCI peripheral software driver for a RS232 communication with a |
;| hyperterminal in half-duplex mode. |
;| Polling software strategy without error management. |
;| |
;|PIN ALLOCATION: |
;| All SCI pins: RDI, TDO |
;+------------------------------------------------------------------------------+
TITLE "sci264.ASM"
; This title will appear on each
; page of the listing file
MOTOROLA ; This directive forces the Motorola
; format for the assembly (default)
;+------------------------------------------------------------------------------+
;| FILES INCLUSION |
;+------------------------------------------------------------------------------+
#INCLUDE "st72264.inc" ; Include st72264 registers and
; Memory mapping file
;+------------------------------------------------------------------------------+
;| DEFINES INCLUSION |
;+------------------------------------------------------------------------------+
; SCI SPEEDS (extended prescalers not
; required for the speeds below):
; #DEFINE BRR_SPEED $C0 ; 38.400 bps: transmission & reception
; #DEFINE BRR_SPEED $C9 ; 19.200 bps: transmission & reception
#DEFINE BRR_SPEED $D2 ; 9.600 bps: transmission & reception
; #DEFINE BRR_SPEED $DB ; 4.800 bps: transmission & reception
; #DEFINE BRR_SPEED $E4 ; 2.400 bps: transmission & reception
; #DEFINE BRR_SPEED $ED ; 1.200 bps: transmission & reception
; SCICR1
#DEFINE CR1_8B_MODE $00 ; 8 bits word
#DEFINE CR1_9B_MODE $50 ; 9 bits word
; MODE SELECTION
#DEFINE CR1_MODE CR1_8B_MODE
; #DEFINE CR1_MODE CR1_9B_MODE
; SCI REGISTER VALUES
#DEFINE CR2_RX_VAL $04 ; Reception only mode without interrupts
#DEFINE CR2_TX_VAL $08 ; Transmission only mode without interrupts
; SCISR BITS DEFINITIONS
#DEFINE TDRE 7 ; Transmit data register empty
#DEFINE TC 6 ; Transmission complete
#DEFINE RDRF 5 ; Received data ready flag
#DEFINE IDLE 4 ; Idle line detect
#DEFINE OR 3 ; Overrun error
#DEFINE NF 2 ; Noise flag
#DEFINE FE 1 ; Framing error.
#DEFINE PE 0 ; Parity error
; SCICR1 BITS DEFINITIONS
#DEFINE R8 7 ; Receive data bit 8
#DEFINE T8 6 ; Transmit data bit 8
#DEFINE SCID 5 ; SCI Disable
#DEFINE M 4 ; Word length
#DEFINE WAKE 3 ; Wake-Up method
#DEFINE PCE 2 ; Parity control
#DEFINE PS 1 ; Parity selection
#DEFINE PIE 0 ; Parity interrupt
; SCICR2 BITS DEFINITIONS
#DEFINE TIE 7 ; Transmitter interrupt enable
#DEFINE TCIE 6 ; Transmission complete interrupt enable
#DEFINE RIE 5 ; Receiver interrupt enable
#DEFINE ILIE 4 ; Idle line interrupt enable
#DEFINE TE 3 ; Transmitter enable
#DEFINE RE 2 ; Receiver enable
#DEFINE RWU 1 ; Receiver wake-up
#DEFINE SBK 0 ; Send break
;+------------------------------------------------------------------------------+
;| RAM VARIABLES |
;+------------------------------------------------------------------------------+
BYTES ; Following addresses are 8-bit long
segment byte at 80-FF 'ram0'
.buff DS.B 4 ; Data buffer
;+------------------------------------------------------------------------------+
;| ROM CONSTANTS |
;+------------------------------------------------------------------------------+
WORDS
segment 'rom'
.Nb DC.B 4 ; Number of bytes to transmit and receive
.buff_def DC.B "tset" ; Initial value of buffer
;+------------------------------------------------------------------------------+
;| MAIN SECTION |
;+------------------------------------------------------------------------------+
.main
; Initialisations
call port_init
call SCI_init
call buff_init
; Main loop, transmission and reception
loop call SCI_Tx
call SCI_Rx
jra loop
;+------------------------------------------------------------------------------+
;| SUB-ROUTINES SECTION |
;+------------------------------------------------------------------------------+
;********************************************************************************
;+------------------------------------------------------------------------------+
;| |
;| ST7 PORT INITIALISATION |
;| |
;+------------------------------------------------------------------------------+
;|ROUTINE DESCRIPTION: |
;| This routine initialises the used pins of the ST7 |
;| |
;|INPUT PARAMETERS: |
;| None |
;| |
;|INTERNAL PARAMETERS: |
;| None |
;| |
;|OUTPUT PARAMETERS: |
;| None |
;+------------------------------------------------------------------------------+
.port_init
bres PADDR,#5 ; PA5 and PA7 must be defined as INPUTS
bres PADDR,#7
bres PAOR,#5
bres PAOR,#7
ret
;********************************************************************************
;********************************************************************************
;+------------------------------------------------------------------------------+
;| |
;| SCI INITIALISATION |
;| |
;+------------------------------------------------------------------------------+
;|ROUTINE DESCRIPTION: |
;| This routine initialises the SCI peripheral |
;| |
;|INPUT PARAMETERS: |
;| None |
;| |
;|INTERNAL PARAMETERS: |
;| A (accumulator) |
;| |
;|OUTPUT PARAMETERS: |
;| None |
;+------------------------------------------------------------------------------+
.SCI_init
clr SCICR1 ; Force reset status of the CR1
clr SCICR2 ; Force reset status of the CR2
ld A,SCISR ; Touch registers to remove pending its
ld A,SCIDR
ld A,#BRR_SPEED
ld SCIBRR,A ; Set data receive & transmit SCI speed
ld A,#CR1_MODE ; Set selected mode of control register 1
ld SCICR1,A
ret
;********************************************************************************
;********************************************************************************
;+------------------------------------------------------------------------------+
;| |
;| SCI TRANSMISSION |
;| |
;+------------------------------------------------------------------------------+
;|ROUTINE DESCRIPTION: |
;| This routine transmits the data buffer via SCI |
;| |
;|INPUT PARAMETERS: |
;| Buffer @, Number of data bytes to transmit |
;| |
;|INTERNAL PARAMETERS: |
;| A (accumulator) |
;| |
;|OUTPUT PARAMETERS: |
;| None |
;+------------------------------------------------------------------------------+
.SCI_Tx
ld A,#CR2_TX_VAL ; Set SCI peripheral in transmission mode
ld SCICR2,A
; The reception is disabled, no data must be sent to the ST7. If data are
; to be received during this part, the RE bit must be set and the user will
; have to use interruptions. If these advises are not respected,a wrong byte
; might be detected when going back in reception mode.
ld X,Nb ; X = number of bytes to transmit
dec X ; X --> last address of the data buffer
cont_t ld A,(buff,X) ; Check the next byte of the data buffer
; to be transmitted
ld SCIDR,A ; Send data byte through SCI bus
wait_t btjf SCISR,#TDRE,wait_t ; Wait for the end of transmission
; of the byte
dec X ; Decrement the relative address
jrpl cont_t ; When X is negative, all bytes have
; been sent, end of loop
ret
;********************************************************************************
;********************************************************************************
;+------------------------------------------------------------------------------+
;| |
;| SCI RECEPTION |
;| |
;+------------------------------------------------------------------------------+
;|ROUTINE DESCRIPTION: |
;| This routine receives in the data buffer via SCI |
;| |
;|INPUT PARAMETERS: |
;| Buffer @, Number of data bytes to receive |
;| |
;|INTERNAL PARAMETERS: |
;| A (accumulator) |
;| |
;|OUTPUT PARAMETERS: |
;| None |
;+------------------------------------------------------------------------------+
.SCI_Rx
ld A,#CR2_RX_VAL ; Set SCI peripheral in reception mode
ld SCICR2,A
ld X,Nb ; X = number of data bytes to receive
dec X ; X --> last address of the data buffer
cont_r
wait_r btjf SCISR,#RDRF,wait_r ; Wait for reception of a new byte
ld A,SCIDR ; Put the new byte in the data buffer
ld (buff,X),A
dec X ; Decrement the relative address
jrpl cont_r ; When X is negative, all bytes have
; been received, end of loop
ret
;********************************************************************************
;********************************************************************************
;+------------------------------------------------------------------------------+
;| |
;| SCI BUFFER INITIALISATION |
;| |
;+------------------------------------------------------------------------------+
;|ROUTINE DESCRIPTION: |
;| This routine initializes the data buffer |
;| |
;|INPUT PARAMETERS: |
;| buff_def, number of bytes |
;| |
;|INTERNAL PARAMETERS: |
;| A (accumulator) |
;| |
;|OUTPUT PARAMETERS: |
;| None |
;+------------------------------------------------------------------------------+
.buff_init
ld X,Nb ; Load in X the number of data bytes
dec X ; X --> last address of the data buffer
cont_b ld A,(buff_def,X)
ld (buff,X),A ; Put in buff the value of buff_def
dec X ; Decrement the relative address
jrpl cont_b ; When X is negative,
; initialisation done, end of loop
ret
;********************************************************************************
;+------------------------------------------------------------------------------+
;| INTERRUPT SUB-ROUTINES SECTION |
;+------------------------------------------------------------------------------+
.dummy iret ; Empty subroutine
.sci_rt iret ; SPI Interrupt
;+------------------------------------------------------------------------------+
;| INTERRUPT VECTORS MAPPING |
;+------------------------------------------------------------------------------+
segment 'vectit'
DC.W dummy ;FFE0-FFE1h location
DC.W dummy ;FFE2-FFE3h location
.i2c_it DC.W dummy ;FFE4-FFE5h location
.sci_it DC.W sci_rt ;FFE6-FFE7h location
DC.W dummy ;FFE8-FFE9h location
DC.W dummy ;FFEA-FFEBh location
DC.W dummy ;FFEC-FFEDh location
.timb_it DC.W dummy ;FFEE-FFEFh location
DC.W dummy ;FFF0-FFF1h location
.tima_it DC.W dummy ;FFF2-FFF3h location
.spi_it DC.W dummy ;FFF4-FFF5h location
DC.W dummy ;FFF6-FFF7h location
.ext1_it DC.W dummy ;FFF8-FFF9h location
.ext0_it DC.W dummy ;FFFA-FFFBh location
.softit DC.W dummy ;FFFC-FFFDh location
.reset DC.W main ;FFFE-FFFFh location
END
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