?? skl_mb_qpel_mmx.asm
字號:
H_PASS_16 1, 0, 0Skl_H_Pass_Avrg_Up_16_Copy_Rnd0_MMX: H_PASS_16 2, 0, 0;//////////////////////////////////////////////////////////////////////;// 8x? copy FunctionsSkl_H_Pass_8_Copy_Rnd1_MMX: H_PASS_8 0, 0, 1Skl_H_Pass_Avrg_8_Copy_Rnd1_MMX: H_PASS_8 1, 0, 1Skl_H_Pass_Avrg_Up_8_Copy_Rnd1_MMX: H_PASS_8 2, 0, 1Skl_H_Pass_8_Copy_Rnd0_MMX: H_PASS_8 0, 0, 0Skl_H_Pass_Avrg_8_Copy_Rnd0_MMX: H_PASS_8 1, 0, 0Skl_H_Pass_Avrg_Up_8_Copy_Rnd0_MMX: H_PASS_8 2, 0, 0;//////////////////////////////////////////////////////////////////////;// 16x? avrg Functions;Skl_H_Pass_16_Add_Rnd1_MMX:; H_PASS_16 0, 1, 1;Skl_H_Pass_Avrg_16_Add_Rnd1_MMX:; H_PASS_16 1, 1, 1;Skl_H_Pass_Avrg_Up_16_Add_Rnd1_MMX:; H_PASS_16 2, 1, 1Skl_H_Pass_16_Add_Rnd0_MMX: H_PASS_16 0, 1, 0Skl_H_Pass_Avrg_16_Add_Rnd0_MMX: H_PASS_16 1, 1, 0Skl_H_Pass_Avrg_Up_16_Add_Rnd0_MMX: H_PASS_16 2, 1, 0;//////////////////////////////////////////////////////////////////////;// 8x? avrg Functions;Skl_H_Pass_8_Add_Rnd1_MMX:; H_PASS_8 0, 1, 1;Skl_H_Pass_Avrg_8_Add_Rnd1_MMX:; H_PASS_8 1, 1, 1;Skl_H_Pass_Avrg_Up_8_Add_Rnd1_MMX:; H_PASS_8 2, 1, 1Skl_H_Pass_8_Add_Rnd0_MMX: H_PASS_8 0, 1, 0Skl_H_Pass_Avrg_8_Add_Rnd0_MMX: H_PASS_8 1, 1, 0Skl_H_Pass_Avrg_Up_8_Add_Rnd0_MMX: H_PASS_8 2, 1, 0;//////////////////////////////////////////////////////////////////////;//;// All vertical passes;//;//////////////////////////////////////////////////////////////////////%macro V_LOAD 1 ; %1=Last? movd mm4, [edx] pxor mm6, mm6%if (%1==0) add edx, ebp%endif punpcklbw mm4, mm6%endmacro%macro V_ACC1 2 ; %1:reg; 2:tap pmullw mm4, [%2] paddw %1, mm4%endmacro%macro V_ACC2 4 ; %1-%2: regs, %3-%4: taps movq mm5, mm4 movq mm6, mm4 pmullw mm5, [%3] pmullw mm6, [%4] paddw %1, mm5 paddw %2, mm6%endmacro%macro V_ACC2l 4 ; %1-%2: regs, %3-%4: taps movq mm5, mm4 pmullw mm5, [%3] pmullw mm4, [%4] paddw %1, mm5 paddw %2, mm4%endmacro%macro V_ACC4 8 ; %1-%4: regs, %5-%8: taps V_ACC2 %1,%2, %5,%6 V_ACC2l %3,%4, %7,%8%endmacro%macro V_MIX 3 ; %1:dst-reg, %2:src, %3: rounder pxor mm6, mm6 movq mm4, [%2] punpcklbw %1, mm6 punpcklbw mm4, mm6 paddusw %1, mm4 paddusw %1, [%3] psrlw %1, 1 packuswb %1, %1%endmacro%macro V_STORE 4 ; %1-%2: mix ops, %3: reg, %4:last? psraw %3, 5 packuswb %3, %3%if (%1==1) V_MIX %3, esi, ebx add esi, ebp%elif (%1==2) add esi, ebp V_MIX %3, esi, ebx%endif%if (%2==1) V_MIX %3, edi, Rounder1_MMX%endif movd eax, %3 mov [edi], eax%if (%4==0) add edi, ebp%endif%endmacro;//////////////////////////////////////////////////////////////////////%macro V_PASS_16 3 ; %1:src-op (0=NONE,1=AVRG,2=AVRG-UP), %2:dst-op (NONE/AVRG), %3:rounder%if (%2==0) && (%1==0) PROLOG_NO_AVRG %3%else PROLOG_AVRG %3%endif ; we process one stripe of 4x16 pixel each time. ; the size (3rd argument) is meant to be a multiple of 4 ; mm0..mm3 serves as a 4x4 delay line.Loop push edi push esi ; esi is preserved for src-mixing mov edx, esi ; ouput rows [0..3], from input rows [0..8] movq mm0, mm7 movq mm1, mm7 movq mm2, mm7 movq mm3, mm7 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C14, FIR_Cm3, FIR_C2, FIR_Cm1 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C23, FIR_C19, FIR_Cm6, FIR_C3 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm7, FIR_C20, FIR_C20, FIR_Cm6 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C3, FIR_Cm6, FIR_C20, FIR_C20 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm1, FIR_C3, FIR_Cm6, FIR_C20 V_STORE %1, %2, mm0, 0 V_LOAD 0 V_ACC2 mm1, mm2, FIR_Cm1, FIR_C3 V_ACC1 mm3, FIR_Cm6 V_STORE %1, %2, mm1, 0 V_LOAD 0 V_ACC2l mm2, mm3, FIR_Cm1, FIR_C3 V_STORE %1, %2, mm2, 0 V_LOAD 1 V_ACC1 mm3, FIR_Cm1 V_STORE %1, %2, mm3, 0 ; ouput rows [4..7], from input rows [1..11] (!!) mov esi, [esp] lea edx, [esi+ebp] lea esi, [esi+4*ebp] ; for src-mixing push esi ; this will be the new value for next round movq mm0, mm7 movq mm1, mm7 movq mm2, mm7 movq mm3, mm7 V_LOAD 0 V_ACC1 mm0, FIR_Cm1 V_LOAD 0 V_ACC2l mm0, mm1, FIR_C3, FIR_Cm1 V_LOAD 0 V_ACC2 mm0, mm1, FIR_Cm6, FIR_C3 V_ACC1 mm2, FIR_Cm1 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C20, FIR_Cm6, FIR_C3, FIR_Cm1 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C20, FIR_C20, FIR_Cm6, FIR_C3 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm6, FIR_C20, FIR_C20, FIR_Cm6 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C3, FIR_Cm6, FIR_C20, FIR_C20 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm1, FIR_C3, FIR_Cm6, FIR_C20 V_STORE %1, %2, mm0, 0 V_LOAD 0 V_ACC2 mm1, mm2, FIR_Cm1, FIR_C3 V_ACC1 mm3, FIR_Cm6 V_STORE %1, %2, mm1, 0 V_LOAD 0 V_ACC2l mm2, mm3, FIR_Cm1, FIR_C3 V_STORE %1, %2, mm2, 0 V_LOAD 1 V_ACC1 mm3, FIR_Cm1 V_STORE %1, %2, mm3, 0 ; ouput rows [8..11], from input rows [5..15] pop esi lea edx, [esi+ebp] lea esi, [esi+4*ebp] ; for src-mixing push esi ; this will be the new value for next round movq mm0, mm7 movq mm1, mm7 movq mm2, mm7 movq mm3, mm7 V_LOAD 0 V_ACC1 mm0, FIR_Cm1 V_LOAD 0 V_ACC2l mm0, mm1, FIR_C3, FIR_Cm1 V_LOAD 0 V_ACC2 mm0, mm1, FIR_Cm6, FIR_C3 V_ACC1 mm2, FIR_Cm1 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C20, FIR_Cm6, FIR_C3, FIR_Cm1 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C20, FIR_C20, FIR_Cm6, FIR_C3 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm6, FIR_C20, FIR_C20, FIR_Cm6 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C3, FIR_Cm6, FIR_C20, FIR_C20 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm1, FIR_C3, FIR_Cm6, FIR_C20 V_STORE %1, %2, mm0, 0 V_LOAD 0 V_ACC2 mm1, mm2, FIR_Cm1, FIR_C3 V_ACC1 mm3, FIR_Cm6 V_STORE %1, %2, mm1, 0 V_LOAD 0 V_ACC2l mm2, mm3, FIR_Cm1, FIR_C3 V_STORE %1, %2, mm2, 0 V_LOAD 1 V_ACC1 mm3, FIR_Cm1 V_STORE %1, %2, mm3, 0 ; ouput rows [12..15], from input rows [9.16] pop esi lea edx, [esi+ebp]%if (%1!=0) lea esi, [esi+4*ebp] ; for src-mixing%endif movq mm0, mm7 movq mm1, mm7 movq mm2, mm7 movq mm3, mm7 V_LOAD 0 V_ACC1 mm3, FIR_Cm1 V_LOAD 0 V_ACC2l mm2, mm3, FIR_Cm1, FIR_C3 V_LOAD 0 V_ACC2 mm1, mm2, FIR_Cm1, FIR_C3 V_ACC1 mm3, FIR_Cm6 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm1, FIR_C3, FIR_Cm6, FIR_C20 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C3, FIR_Cm6, FIR_C20, FIR_C20 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm7, FIR_C20, FIR_C20, FIR_Cm6 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C23, FIR_C19, FIR_Cm6, FIR_C3 V_LOAD 1 V_ACC4 mm0, mm1, mm2, mm3, FIR_C14, FIR_Cm3, FIR_C2, FIR_Cm1 V_STORE %1, %2, mm3, 0 V_STORE %1, %2, mm2, 0 V_STORE %1, %2, mm1, 0 V_STORE %1, %2, mm0, 1 ; ... next 4 columns pop esi pop edi add esi, 4 add edi, 4 sub ecx, 4 jg .Loop%if (%2==0) && (%1==0) EPILOG_NO_AVRG%else EPILOG_AVRG%endif%endmacro;//////////////////////////////////////////////////////////////////////%macro V_PASS_8 3 ; %1:src-op (0=NONE,1=AVRG,2=AVRG-UP), %2:dst-op (NONE/AVRG), %3:rounder%if (%2==0) && (%1==0) PROLOG_NO_AVRG %3%else PROLOG_AVRG %3%endif ; we process one stripe of 4x8 pixel each time ; the size (3rd argument) is meant to be a multiple of 4 ; mm0..mm3 serves as a 4x4 delay line.Loop push edi push esi ; esi is preserved for src-mixing mov edx, esi ; ouput rows [0..3], from input rows [0..8] movq mm0, mm7 movq mm1, mm7 movq mm2, mm7 movq mm3, mm7 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C14, FIR_Cm3, FIR_C2, FIR_Cm1 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C23, FIR_C19, FIR_Cm6, FIR_C3 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm7, FIR_C20, FIR_C20, FIR_Cm6 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C3, FIR_Cm6, FIR_C20, FIR_C20 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm1, FIR_C3, FIR_Cm6, FIR_C20 V_STORE %1, %2, mm0, 0 V_LOAD 0 V_ACC2 mm1, mm2, FIR_Cm1, FIR_C3 V_ACC1 mm3, FIR_Cm6 V_STORE %1, %2, mm1, 0 V_LOAD 0 V_ACC2l mm2, mm3, FIR_Cm1, FIR_C3 V_STORE %1, %2, mm2, 0 V_LOAD 1 V_ACC1 mm3, FIR_Cm1 V_STORE %1, %2, mm3, 0 ; ouput rows [4..7], from input rows [1..9] mov esi, [esp] lea edx, [esi+ebp]%if (%1!=0) lea esi, [esi+4*ebp] ; for src-mixing%endif movq mm0, mm7 movq mm1, mm7 movq mm2, mm7 movq mm3, mm7 V_LOAD 0 V_ACC1 mm3, FIR_Cm1 V_LOAD 0 V_ACC2l mm2, mm3, FIR_Cm1, FIR_C3 V_LOAD 0 V_ACC2 mm1, mm2, FIR_Cm1, FIR_C3 V_ACC1 mm3, FIR_Cm6 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm1, FIR_C3, FIR_Cm6, FIR_C20 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C3, FIR_Cm6, FIR_C20, FIR_C20 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_Cm7, FIR_C20, FIR_C20, FIR_Cm6 V_LOAD 0 V_ACC4 mm0, mm1, mm2, mm3, FIR_C23, FIR_C19, FIR_Cm6, FIR_C3 V_LOAD 1 V_ACC4 mm0, mm1, mm2, mm3, FIR_C14, FIR_Cm3, FIR_C2, FIR_Cm1 V_STORE %1, %2, mm3, 0 V_STORE %1, %2, mm2, 0 V_STORE %1, %2, mm1, 0 V_STORE %1, %2, mm0, 1 ; ... next 4 columns pop esi pop edi add esi, 4 add edi, 4 sub ecx, 4 jg .Loop%if (%2==0) && (%1==0) EPILOG_NO_AVRG%else EPILOG_AVRG%endif%endmacro;//////////////////////////////////////////////////////////////////////;// 16x? copy FunctionsSkl_V_Pass_16_Copy_Rnd1_MMX: V_PASS_16 0, 0, 1Skl_V_Pass_Avrg_16_Copy_Rnd1_MMX: V_PASS_16 1, 0, 1Skl_V_Pass_Avrg_Up_16_Copy_Rnd1_MMX: V_PASS_16 2, 0, 1Skl_V_Pass_16_Copy_Rnd0_MMX: V_PASS_16 0, 0, 0Skl_V_Pass_Avrg_16_Copy_Rnd0_MMX: V_PASS_16 1, 0, 0Skl_V_Pass_Avrg_Up_16_Copy_Rnd0_MMX: V_PASS_16 2, 0, 0;//////////////////////////////////////////////////////////////////////;// 8x? copy FunctionsSkl_V_Pass_8_Copy_Rnd1_MMX: V_PASS_8 0, 0, 1Skl_V_Pass_Avrg_8_Copy_Rnd1_MMX: V_PASS_8 1, 0, 1Skl_V_Pass_Avrg_Up_8_Copy_Rnd1_MMX: V_PASS_8 2, 0, 1Skl_V_Pass_8_Copy_Rnd0_MMX: V_PASS_8 0, 0, 0Skl_V_Pass_Avrg_8_Copy_Rnd0_MMX: V_PASS_8 1, 0, 0Skl_V_Pass_Avrg_Up_8_Copy_Rnd0_MMX: V_PASS_8 2, 0, 0;//////////////////////////////////////////////////////////////////////;// 16x? avrg Functions;Skl_V_Pass_16_Add_Rnd1_MMX:; V_PASS_16 0, 1, 1;Skl_V_Pass_Avrg_16_Add_Rnd1_MMX:; V_PASS_16 1, 1, 1;Skl_V_Pass_Avrg_Up_16_Add_Rnd1_MMX:; V_PASS_16 2, 1, 1Skl_V_Pass_16_Add_Rnd0_MMX: V_PASS_16 0, 1, 0Skl_V_Pass_Avrg_16_Add_Rnd0_MMX: V_PASS_16 1, 1, 0Skl_V_Pass_Avrg_Up_16_Add_Rnd0_MMX: V_PASS_16 2, 1, 0;//////////////////////////////////////////////////////////////////////;// 8x? avrg Functions;Skl_V_Pass_8_Add_Rnd1_MMX:; V_PASS_8 0, 1, 1;Skl_V_Pass_Avrg_8_Add_Rnd1_MMX:; V_PASS_8 1, 1, 1;Skl_V_Pass_Avrg_Up_8_Add_Rnd1_MMX:; V_PASS_8 2, 1, 1Skl_V_Pass_8_Add_Rnd0_MMX: V_PASS_8 0, 1, 0Skl_V_Pass_Avrg_8_Add_Rnd0_MMX: V_PASS_8 1, 1, 0Skl_V_Pass_Avrg_Up_8_Add_Rnd0_MMX: V_PASS_8 2, 1, 0;//////////////////////////////////////////////////////////////////////?? 快捷鍵說明
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