?? dma4.c
字號:
MCBSP_RCR2_RFRLEN2_DEFAULT,
MCBSP_RCR2_RWDLEN2_16BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_0BIT
), /* RCR2 */
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_DEFAULT,
MCBSP_XCR1_XWDLEN1_32BIT
), /* XCR1 */
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(0),
MCBSP_XCR2_XWDLEN2_32BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_YES,
MCBSP_XCR2_XDATDLY_0BIT
), /* XCR2 */
MCBSP_SRGR1_FWID_OF(0),
MCBSP_SRGR1_CLKGDV_OF(1)
), /* SRGR1 */
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_INTERNAL,
MCBSP_SRGR2_FSGM_DEFAULT,
MCBSP_SRGR2_FPER_DEFAULT
), /* SRGR2 */
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_DEFAULT,
MCBSP_PCR_RIOEN_DEFAULT,
MCBSP_PCR_FSXM_EXTERNAL,
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
MCBSP_PCR_CLKXM_INPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_FSXP_ACTIVELOW,
MCBSP_PCR_FSRP_ACTIVELOW,
MCBSP_PCR_CLKXP_RISING,
MCBSP_PCR_CLKRP_RISING
), /* PCR */
0x0000u, /* RCERA */
0x0000u, /* RCERB */
0x0000u, /* XCERA */
0x0000u, /* XCERB */
};
/* Create a configuration structure for DMA channel 5 using */
/* predefined CSL macros and symbolic constants */
DMA_Config my_dmaConfigCha5 = {
1, /* Priority */
DMA_DMMCR_RMK(
DMA_DMMCR_DINM_ON,
DMA_DMMCR_IMOD_HALF_AND_FULL,
DMA_DMMCR_CTMOD_ABU,
// DMA_DMMCR_CTMOD_MULTIFRAME,
DMA_DMMCR_SLAXS_OFF,
DMA_DMMCR_SIND_DMIDX0,
DMA_DMMCR_DMS_DATA,
DMA_DMMCR_DLAXS_OFF,
DMA_DMMCR_DIND_NOMOD,
DMA_DMMCR_DMD_DATA
), /* DMMCR */
DMA_DMSFC_RMK(
DMA_DMSFC_DSYN_XEVT0,
DMA_DMSFC_DBLW_ON, /*32bit Mode*/
DMA_DMSFC_FRAMECNT_OF(0)
), /* DMSFC */
(DMA_AdrPtr)&src[0], /* DMSRC */
(DMA_AdrPtr)MCBSP_ADDR(DXR20), /* DMDST */
(Uint16)(Nm2) /* DMCTR = buffsize */
};
/* Create configuration structure for DMA channel 4 using */
/* predefined CSL macros and symbolic constants */
DMA_Config my_dmaConfigCha4 = {
0, /* Set Priority */
DMA_DMMCR_RMK(
DMA_DMMCR_AUTOINIT_OFF,
DMA_DMMCR_DINM_ON,
DMA_DMMCR_IMOD_HALF_AND_FULL,
DMA_DMMCR_CTMOD_ABU,
// DMA_DMMCR_CTMOD_MULTIFRAME,
DMA_DMMCR_SLAXS_OFF,
DMA_DMMCR_SIND_NOMOD,
DMA_DMMCR_DMS_DATA,
DMA_DMMCR_DLAXS_OFF,
DMA_DMMCR_DIND_DMIDX0,
DMA_DMMCR_DMD_DATA
), /* DMMCR */
DMA_DMSFC_RMK(
DMA_DMSFC_DSYN_REVT0,
DMA_DMSFC_DBLW_ON,
DMA_DMSFC_FRAMECNT_OF(0)
), /* DMSFC */
(DMA_AdrPtr)MCBSP_ADDR(DRR20), /* DMSRC */
(DMA_AdrPtr)&dst[0], /* DMDST */
(Uint16)(Nm2) /* DMCTR = buffsize */
};
/* Global declarations */
DMA_Handle myhDmaCha4;
DMA_Handle myhDmaCha5;
MCBSP_Handle myhMcbsp1;
volatile Uint16 WaitForDmaRec = TRUE;
volatile Uint16 WaitForDmaSend= TRUE;
interrupt void hMcbsp1RcvIsr(void);
interrupt void hMcbsp1XmtIsr(void);
interrupt void dmaCha5Isr(void);
interrupt void dmaCha4Isr(void);
void taskFunc(void);
Uint16 RcvFlag;
Uint16 XmtFlag;
void DelayModule(Uint16 DelayNum)
{
Uint16 i,j;
for(i=0;i<100;i++)
{
for(j=0;j<DelayNum;j++);
}
}
/*----------------------------------------------------------------------------*/
void main() {
Uint16 InitNum,kk;
/* Initialize CSL library, this step is required */
CSL_init();
/* Initialize IVPTR to start of vector table */
IRQ_setVecs((Uint16)(&VECSTART));
*SWWSR=0x0400;
asm(" RSBX XF");
//asm(" STM #0a8H,PMST");
/* Initialize send and receive buffers */
for(InitNum=0;InitNum<N;InitNum++)
{
src[InitNum]=0;dst[InitNum]=0;
}
for (kk=0; kk<Nd4;kk++) {TargetLf1[kk]=0;}
for (kk=0; kk<Nd4;kk++) {TargetLf2[kk]=0;}
for (kk=0; kk<Nd4;kk++) {TargetRf1[kk]=0;}
for (kk=0; kk<Nd4;kk++) {TargetRf2[kk]=0;}
for (kk=0; kk<64; kk++) {db[kk] = 0;} // clear delay buffer (a must)
for (kk=0; kk<64; kk++) {dbfhl2[kk] = 0;}
for (kk=0; kk<64; kk++) {db2[kk] = 0;}
for (kk=0; kk<64; kk++) {dbfhr2[kk] = 0;}
/* Call example function */
taskFunc();
}
/*----------------------------------------------------------------------------*/
void ProcessSub(void)
{
Uint16 pCnt,ii;
//************************************//
for(pCnt=0;pCnt<Nd4;pCnt++)
{
dsttemp=(Dis[pCnt*2+1]&0x80000000);
if(dsttemp==0x80000000)
{
dsttemp=Dis[pCnt*2+1];
dsttemp=(~dsttemp)+1>>16;
LchIn[pCnt]=~dsttemp+1;
}
else
{
dsttemp=Dis[pCnt*2+1];
LchIn[pCnt]=(dsttemp)>>16;
}
}
/* compute */
fir(LchIn, h,TargetLf1, &dbptr, 64, Nd4);
fir(LchIn, fhl2,TargetLf2, &ptrfhl2, 64, Nd4);
for(ii=0;ii<Nd4;ii++)
{LchIn[ii]=(TargetLf1[ii]>>1)*3+TargetLf2[ii];}
for(pCnt=0;pCnt<Nd4;pCnt++)
{
Dis[pCnt*2+1]=LchIn[pCnt];
Dis[pCnt*2+1]<<=16;
}
////////////*****************////////////////
for(pCnt=0;pCnt<Nd4;pCnt++)
{
dsttemp=(Dis[pCnt*2]&0x80000000);
if(dsttemp==0x80000000)
{
dsttemp=Dis[pCnt*2];
dsttemp=(~dsttemp)>>16;
RchIn[pCnt]=~dsttemp;
}
else
{
dsttemp=Dis[pCnt*2];
RchIn[pCnt]=(dsttemp)>>16;
}
}
/* compute */
fir(RchIn,h2,TargetRf1,&dbptr2,64,Nd4);
fir(RchIn,fhr2,TargetRf2, &ptrfhr2, 64, Nd4);
for(ii=0;ii<Nd4;ii++)
{RchIn[ii]=(TargetRf1[ii]>>1)*3+TargetRf2[ii];}
for(pCnt=0;pCnt<Nd4;pCnt++)
{
Dis[pCnt*2]=RchIn[pCnt];
Dis[pCnt*2]<<=16;
}
//****************************************//
}
void taskFunc() {
MCBSP_Handle myhMcbsp;
Uint16 hMcbsp1RcvId,hMcbsp1XmtId;
Uint16 cha4EventId, cha5EventId;
Uint16 CopyCnt;
/* Temporarily disable all maskable interrupts */
/* keeping old status of INTM bit */
IRQ_globalDisable();
/* Open MCBSP channel 0 */
myhMcbsp = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
/* Open MCBSP channel 1 */
myhMcbsp1= MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
/* Write configuration values to MCBSP 0 control registers */
MCBSP_config(myhMcbsp, &my_mcbspConfig);
/* Write configuration values to MCBSP 1 control registers */
MCBSP_config(myhMcbsp1, &my_mcbspConfig1);
hMcbsp1RcvId=MCBSP_getRcvEventId(myhMcbsp1);
hMcbsp1XmtId=MCBSP_getXmtEventId(myhMcbsp1);
/* Open DMA channels 4 & 5*/
myhDmaCha4 = DMA_open(DMA_CHA4, 0);
myhDmaCha5 = DMA_open(DMA_CHA5, 0);
/* Write configuration structure values to DMa control registers */
DMA_config(myhDmaCha4, &my_dmaConfigCha4);
DMA_config(myhDmaCha5, &my_dmaConfigCha5);
/* Get Event ID's associated with DMA channels */
cha4EventId = DMA_getEventId(myhDmaCha4);
cha5EventId = DMA_getEventId(myhDmaCha5);
/* the interrupt selector value in DMA priority and enable */
/* register, DMPREC */
DMA_FSET(DMPREC,INTOSEL,0);
/* Set FREE bit in DMPREC to enable free run on DMA */
DMA_FSET(DMPREC,FREE,1);
/* Clear all pending maskable interrupts */
CHIP_RSET(IFR,0xFFFFu);
/* Enable interrupts for DMA channels 4 & 5*/
IRQ_enable(cha4EventId);
IRQ_enable(cha5EventId);
/* Map DMA interrupts for use with dispatcher */
IRQ_plug(cha4EventId,&dmaCha4Isr);
IRQ_plug(cha5EventId,&dmaCha5Isr);
/* Set value of Global Index Register , DMIDX0 */
DMA_RSET(DMIDX0,1);
/* Enable all maskable interrupts, INTM = 0 */
//IRQ_globalEnable();
/* Start DMA */
DMA_start(myhDmaCha5);
DMA_start(myhDmaCha4);
IRQ_enable(hMcbsp1RcvId);
IRQ_enable(hMcbsp1XmtId);
IRQ_plug(hMcbsp1RcvId,&hMcbsp1RcvIsr);
IRQ_plug(hMcbsp1XmtId,&hMcbsp1XmtIsr);
/* Start Sample Rate Generator and Enable Frame Sync */
MCBSP_start(myhMcbsp,
MCBSP_SRGR_START|MCBSP_SRGR_FRAMESYNC ,
0x200
);
/* Take MCBSP transmit and receive out of reset */
MCBSP_start(myhMcbsp,
MCBSP_RCV_START|MCBSP_XMIT_START,
0x200
);
/* Start Sample Rate Generator and Enable Frame Sync */
MCBSP_start(myhMcbsp1,
MCBSP_SRGR_START|MCBSP_SRGR_FRAMESYNC , //
0x200
);
/* Take MCBSP transmit and receive out of reset */
MCBSP_start(myhMcbsp1,
MCBSP_RCV_START|MCBSP_XMIT_START,
0x200
);
/* Enable all maskable interrupts, INTM = 0 */
IRQ_globalEnable();
/* Wait for Transfer to Complete */
while(1)
{
if(WaitForDmaRec==0)
{
WaitForDmaRec=1;
PingPong=(PingPong+1)&0x01; /*PingPong=0,Ping Status;PingPong=1,Pong*/
if(PingPong==0)
{
for(CopyCnt=0;CopyCnt<Nd2;CopyCnt++)
{
Dis[CopyCnt]=dst[CopyCnt];
}
}
else
{
for(CopyCnt=Nd2;CopyCnt<N;CopyCnt++)
{
Dis[CopyCnt-Nd2]=dst[CopyCnt];
}
}
//DelayModule(240);
ProcessSub();
if(PingPong==0)
{
for(CopyCnt=0;CopyCnt<Nd2;CopyCnt++)
{
src[CopyCnt]=Dis[CopyCnt];
}
}
else
{
for(CopyCnt=Nd2;CopyCnt<N;CopyCnt++)
{
src[CopyCnt]=Dis[CopyCnt-Nd2];
}
}
}
}
}
/* DMA Channel ISRs, these functions will be called by DSP/BIOS dispatcher */
/*----------------------------------------------------------------------------*/
interrupt void dmaCha5Isr(void){
WaitForDmaSend= 0;
}
/*----------------------------------------------------------------------------*/
interrupt void dmaCha4Isr(void) {
WaitForDmaRec = 0;
}
Uint16 CmdRcv;
interrupt void hMcbsp1RcvIsr(void){
RcvFlag=1;
XmtFlag=0;
//CmdRcv=MCBSP_read16(myhMcbsp1);
}
interrupt void hMcbsp1XmtIsr(void){
RcvFlag=0;
XmtFlag=1;
//MCBSP_write32(myhMcbsp1,0x12345789);
}
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