?? cllock.lss
字號:
cllock.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000338 00000000 00000000 00000094 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .data 00000000 00800060 00000338 000003cc 2**0
CONTENTS, ALLOC, LOAD, DATA
2 .bss 0000000f 00800060 00800060 000003cc 2**0
ALLOC
3 .noinit 00000000 0080006f 0080006f 000003cc 2**0
CONTENTS
4 .eeprom 00000000 00810000 00810000 000003cc 2**0
CONTENTS
5 .stab 0000036c 00000000 00000000 000003cc 2**2
CONTENTS, READONLY, DEBUGGING
6 .stabstr 00000084 00000000 00000000 00000738 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_aranges 00000014 00000000 00000000 000007bc 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_pubnames 00000061 00000000 00000000 000007d0 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_info 000001b6 00000000 00000000 00000831 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_abbrev 000000df 00000000 00000000 000009e7 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_line 000001ba 00000000 00000000 00000ac6 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_str 000000fb 00000000 00000000 00000c80 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <__vectors>:
0: 0c 94 33 00 jmp 0x66 <__init>
4: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
8: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
c: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
10: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
14: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
18: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
1c: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
20: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
24: 0c 94 58 00 jmp 0xb0 <__vector_9>
28: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
2c: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
30: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
34: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
38: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
3c: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
40: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
44: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
48: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
4c: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
50: 0c 94 4e 00 jmp 0x9c <__bad_interrupt>
00000054 <SegCode>:
54: 3f 06 5b 4f 66 6d 7d 07 7f 6f 77 7c 39 5e 79 71 ?.[Ofm}..ow|9^yq
64: 00 40 .@
00000066 <__init>:
66: 11 24 eor r1, r1
68: 1f be out 0x3f, r1 ; 63
6a: cf e5 ldi r28, 0x5F ; 95
6c: d4 e0 ldi r29, 0x04 ; 4
6e: de bf out 0x3e, r29 ; 62
70: cd bf out 0x3d, r28 ; 61
00000072 <__do_copy_data>:
72: 10 e0 ldi r17, 0x00 ; 0
74: a0 e6 ldi r26, 0x60 ; 96
76: b0 e0 ldi r27, 0x00 ; 0
78: e8 e3 ldi r30, 0x38 ; 56
7a: f3 e0 ldi r31, 0x03 ; 3
7c: 02 c0 rjmp .+4 ; 0x82 <.do_copy_data_start>
0000007e <.do_copy_data_loop>:
7e: 05 90 lpm r0, Z+
80: 0d 92 st X+, r0
00000082 <.do_copy_data_start>:
82: a0 36 cpi r26, 0x60 ; 96
84: b1 07 cpc r27, r17
86: d9 f7 brne .-10 ; 0x7e <.do_copy_data_loop>
00000088 <__do_clear_bss>:
88: 10 e0 ldi r17, 0x00 ; 0
8a: a0 e6 ldi r26, 0x60 ; 96
8c: b0 e0 ldi r27, 0x00 ; 0
8e: 01 c0 rjmp .+2 ; 0x92 <.do_clear_bss_start>
00000090 <.do_clear_bss_loop>:
90: 1d 92 st X+, r1
00000092 <.do_clear_bss_start>:
92: af 36 cpi r26, 0x6F ; 111
94: b1 07 cpc r27, r17
96: e1 f7 brne .-8 ; 0x90 <.do_clear_bss_loop>
98: 0c 94 d0 00 jmp 0x1a0 <main>
0000009c <__bad_interrupt>:
9c: 0c 94 00 00 jmp 0x0 <__vectors>
000000a0 <TimerConfig>:
void TimerConfig(void)
{
TCCR0=(1<<CS01)|(1<<CS00); //控制寄存器，工作方式及時鐘選擇
a0: 83 e0 ldi r24, 0x03 ; 3
a2: 83 bf out 0x33, r24 ; 51
TCNT0=(256-250);//計數值
a4: 86 e0 ldi r24, 0x06 ; 6
a6: 82 bf out 0x32, r24 ; 50
TIMSK=0x01; //中斷控制
a8: 81 e0 ldi r24, 0x01 ; 1
aa: 89 bf out 0x39, r24 ; 57
sei();
ac: 78 94 sei
ae: 08 95 ret
000000b0 <__vector_9>:
}
SIGNAL(TIMER0_OVF_vect)
{
b0: 1f 92 push r1
b2: 0f 92 push r0
b4: 0f b6 in r0, 0x3f ; 63
b6: 0f 92 push r0
b8: 11 24 eor r1, r1
ba: 2f 93 push r18
bc: 3f 93 push r19
be: 4f 93 push r20
c0: 8f 93 push r24
c2: 9f 93 push r25
c4: af 93 push r26
c6: bf 93 push r27
c8: ef 93 push r30
ca: ff 93 push r31
static unsigned char i=0;
static unsigned int Cnt=0;
TCNT0=(256-250);
cc: 86 e0 ldi r24, 0x06 ; 6
ce: 82 bf out 0x32, r24 ; 50
PORTB = pgm_read_byte(&SegCode[DisBuffer[i]]);
d0: 40 91 64 00 lds r20, 0x0064
d4: 24 2f mov r18, r20
d6: 33 27 eor r19, r19
d8: f9 01 movw r30, r18
da: e9 59 subi r30, 0x99 ; 153
dc: ff 4f sbci r31, 0xFF ; 255
de: 80 81 ld r24, Z
e0: e8 2f mov r30, r24
e2: ff 27 eor r31, r31
e4: ec 5a subi r30, 0xAC ; 172
e6: ff 4f sbci r31, 0xFF ; 255
e8: 84 91 lpm r24, Z
ea: 88 bb out 0x18, r24 ; 24
PORTA|= (1<<PA4);
ec: dc 9a sbi 0x1b, 4 ; 27
PORTA&=~(1<<PA4);
ee: dc 98 cbi 0x1b, 4 ; 27
PORTB = (1<<i);
f0: 81 e0 ldi r24, 0x01 ; 1
f2: 90 e0 ldi r25, 0x00 ; 0
f4: 02 c0 rjmp .+4 ; 0xfa <__vector_9+0x4a>
f6: 88 0f add r24, r24
f8: 99 1f adc r25, r25
fa: 2a 95 dec r18
fc: e2 f7 brpl .-8 ; 0xf6 <__vector_9+0x46>
fe: 88 bb out 0x18, r24 ; 24
PORTA|= (1<<PA5);
100: dd 9a sbi 0x1b, 5 ; 27
PORTA&=~(1<<PA5);
102: dd 98 cbi 0x1b, 5 ; 27
i++;
104: 84 2f mov r24, r20
106: 8f 5f subi r24, 0xFF ; 255
108: 80 93 64 00 sts 0x0064, r24
if(i==8)
10c: 88 30 cpi r24, 0x08 ; 8
10e: 11 f4 brne .+4 ; 0x114 <__vector_9+0x64>
i=0;
110: 10 92 64 00 sts 0x0064, r1
Cnt++;
114: 80 91 65 00 lds r24, 0x0065
118: 90 91 66 00 lds r25, 0x0066
11c: 01 96 adiw r24, 0x01 ; 1
11e: 90 93 66 00 sts 0x0066, r25
122: 80 93 65 00 sts 0x0065, r24
if(Cnt==500)
126: 84 5f subi r24, 0xF4 ; 244
128: 91 40 sbci r25, 0x01 ; 1
12a: 61 f5 brne .+88 ; 0x184 <__vector_9+0xd4>
{
Cnt=0;
12c: 10 92 66 00 sts 0x0066, r1
130: 10 92 65 00 sts 0x0065, r1
ClockCnt++;
134: 80 91 60 00 lds r24, 0x0060
138: 90 91 61 00 lds r25, 0x0061
13c: a0 91 62 00 lds r26, 0x0062
140: b0 91 63 00 lds r27, 0x0063
144: 01 96 adiw r24, 0x01 ; 1
146: a1 1d adc r26, r1
148: b1 1d adc r27, r1
14a: 80 93 60 00 sts 0x0060, r24
14e: 90 93 61 00 sts 0x0061, r25
152: a0 93 62 00 sts 0x0062, r26
156: b0 93 63 00 sts 0x0063, r27
if(ClockCnt>=86400)
15a: 80 91 60 00 lds r24, 0x0060
15e: 90 91 61 00 lds r25, 0x0061
162: a0 91 62 00 lds r26, 0x0062
166: b0 91 63 00 lds r27, 0x0063
16a: 80 58 subi r24, 0x80 ; 128
16c: 91 45 sbci r25, 0x51 ; 81
16e: a1 40 sbci r26, 0x01 ; 1
170: b0 40 sbci r27, 0x00 ; 0
172: 40 f0 brcs .+16 ; 0x184 <__vector_9+0xd4>
ClockCnt=0;
174: 10 92 60 00 sts 0x0060, r1
178: 10 92 61 00 sts 0x0061, r1
17c: 10 92 62 00 sts 0x0062, r1
180: 10 92 63 00 sts 0x0063, r1
184: ff 91 pop r31
186: ef 91 pop r30
188: bf 91 pop r27
18a: af 91 pop r26
18c: 9f 91 pop r25
18e: 8f 91 pop r24
190: 4f 91 pop r20
192: 3f 91 pop r19
194: 2f 91 pop r18
196: 0f 90 pop r0
198: 0f be out 0x3f, r0 ; 63
19a: 0f 90 pop r0
19c: 1f 90 pop r1
19e: 18 95 reti
000001a0 <main>:
}
}
int main(void)
{
1a0: cf e5 ldi r28, 0x5F ; 95
1a2: d4 e0 ldi r29, 0x04 ; 4
1a4: de bf out 0x3e, r29 ; 62
1a6: cd bf out 0x3d, r28 ; 61
/* Set LED and Smg LE pin as output , databus as output */
DDRA |=(1<<PA4)|(1<<PA5)|(1<<PA6);
1a8: 8a b3 in r24, 0x1a ; 26
1aa: 80 67 ori r24, 0x70 ; 112
1ac: 8a bb out 0x1a, r24 ; 26
DDRB = 0xFF;
1ae: 8f ef ldi r24, 0xFF ; 255
1b0: 87 bb out 0x17, r24 ; 23
/* Off the LED display */
PORTB = 0xFF;
1b2: 88 bb out 0x18, r24 ; 24
PORTA|= (1<<PA6);
1b4: de 9a sbi 0x1b, 6 ; 27
PORTA&=~(1<<PA6);
1b6: de 98 cbi 0x1b, 6 ; 27
TimerConfig();
1b8: 0e 94 50 00 call 0xa0 <TimerConfig>
1bc: c1 e1 ldi r28, 0x11 ; 17
while(1)
{
DisBuffer[0]=ClockCnt/3600/10;
1be: 80 91 60 00 lds r24, 0x0060
1c2: 90 91 61 00 lds r25, 0x0061
1c6: a0 91 62 00 lds r26, 0x0062
1ca: b0 91 63 00 lds r27, 0x0063
1ce: bc 01 movw r22, r24
1d0: cd 01 movw r24, r26
1d2: 20 ea ldi r18, 0xA0 ; 160
1d4: 3c e8 ldi r19, 0x8C ; 140
1d6: 40 e0 ldi r20, 0x00 ; 0
1d8: 50 e0 ldi r21, 0x00 ; 0
1da: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
1de: 20 93 67 00 sts 0x0067, r18
DisBuffer[1]=ClockCnt/3600%10;
1e2: 80 91 60 00 lds r24, 0x0060
1e6: 90 91 61 00 lds r25, 0x0061
1ea: a0 91 62 00 lds r26, 0x0062
1ee: b0 91 63 00 lds r27, 0x0063
1f2: bc 01 movw r22, r24
1f4: cd 01 movw r24, r26
1f6: 20 e1 ldi r18, 0x10 ; 16
1f8: 3e e0 ldi r19, 0x0E ; 14
1fa: 40 e0 ldi r20, 0x00 ; 0
1fc: 50 e0 ldi r21, 0x00 ; 0
1fe: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
202: ca 01 movw r24, r20
204: b9 01 movw r22, r18
206: 2a e0 ldi r18, 0x0A ; 10
208: 30 e0 ldi r19, 0x00 ; 0
20a: 40 e0 ldi r20, 0x00 ; 0
20c: 50 e0 ldi r21, 0x00 ; 0
20e: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
212: dc 01 movw r26, r24
214: cb 01 movw r24, r22
216: 80 93 68 00 sts 0x0068, r24
DisBuffer[2]=LINE;
21a: c0 93 69 00 sts 0x0069, r28
DisBuffer[3]=ClockCnt/60/10%6;
21e: 80 91 60 00 lds r24, 0x0060
222: 90 91 61 00 lds r25, 0x0061
226: a0 91 62 00 lds r26, 0x0062
22a: b0 91 63 00 lds r27, 0x0063
22e: bc 01 movw r22, r24
230: cd 01 movw r24, r26
232: 28 e5 ldi r18, 0x58 ; 88
234: 32 e0 ldi r19, 0x02 ; 2
236: 40 e0 ldi r20, 0x00 ; 0
238: 50 e0 ldi r21, 0x00 ; 0
23a: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
23e: ca 01 movw r24, r20
240: b9 01 movw r22, r18
242: 26 e0 ldi r18, 0x06 ; 6
244: 30 e0 ldi r19, 0x00 ; 0
246: 40 e0 ldi r20, 0x00 ; 0
248: 50 e0 ldi r21, 0x00 ; 0
24a: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
24e: dc 01 movw r26, r24
250: cb 01 movw r24, r22
252: 80 93 6a 00 sts 0x006A, r24
DisBuffer[4]=ClockCnt/60%10;
256: 80 91 60 00 lds r24, 0x0060
25a: 90 91 61 00 lds r25, 0x0061
25e: a0 91 62 00 lds r26, 0x0062
262: b0 91 63 00 lds r27, 0x0063
266: bc 01 movw r22, r24
268: cd 01 movw r24, r26
26a: 2c e3 ldi r18, 0x3C ; 60
26c: 30 e0 ldi r19, 0x00 ; 0
26e: 40 e0 ldi r20, 0x00 ; 0
270: 50 e0 ldi r21, 0x00 ; 0
272: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
276: ca 01 movw r24, r20
278: b9 01 movw r22, r18
27a: 2a e0 ldi r18, 0x0A ; 10
27c: 30 e0 ldi r19, 0x00 ; 0
27e: 40 e0 ldi r20, 0x00 ; 0
280: 50 e0 ldi r21, 0x00 ; 0
282: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
286: dc 01 movw r26, r24
288: cb 01 movw r24, r22
28a: 80 93 6b 00 sts 0x006B, r24
DisBuffer[5]=LINE;
28e: c0 93 6c 00 sts 0x006C, r28
DisBuffer[6]=ClockCnt/10%6;
292: 80 91 60 00 lds r24, 0x0060
296: 90 91 61 00 lds r25, 0x0061
29a: a0 91 62 00 lds r26, 0x0062
29e: b0 91 63 00 lds r27, 0x0063
2a2: bc 01 movw r22, r24
2a4: cd 01 movw r24, r26
2a6: 2a e0 ldi r18, 0x0A ; 10
2a8: 30 e0 ldi r19, 0x00 ; 0
2aa: 40 e0 ldi r20, 0x00 ; 0
2ac: 50 e0 ldi r21, 0x00 ; 0
2ae: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
2b2: ca 01 movw r24, r20
2b4: b9 01 movw r22, r18
2b6: 26 e0 ldi r18, 0x06 ; 6
2b8: 30 e0 ldi r19, 0x00 ; 0
2ba: 40 e0 ldi r20, 0x00 ; 0
2bc: 50 e0 ldi r21, 0x00 ; 0
2be: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
2c2: dc 01 movw r26, r24
2c4: cb 01 movw r24, r22
2c6: 80 93 6d 00 sts 0x006D, r24
DisBuffer[7]=ClockCnt%10;
2ca: 80 91 60 00 lds r24, 0x0060
2ce: 90 91 61 00 lds r25, 0x0061
2d2: a0 91 62 00 lds r26, 0x0062
2d6: b0 91 63 00 lds r27, 0x0063
2da: bc 01 movw r22, r24
2dc: cd 01 movw r24, r26
2de: 2a e0 ldi r18, 0x0A ; 10
2e0: 30 e0 ldi r19, 0x00 ; 0
2e2: 40 e0 ldi r20, 0x00 ; 0
2e4: 50 e0 ldi r21, 0x00 ; 0
2e6: 0e 94 7a 01 call 0x2f4 <__udivmodsi4>
2ea: dc 01 movw r26, r24
2ec: cb 01 movw r24, r22
2ee: 80 93 6e 00 sts 0x006E, r24
2f2: 65 cf rjmp .-310 ; 0x1be <main+0x1e>
000002f4 <__udivmodsi4>:
2f4: a1 e2 ldi r26, 0x21 ; 33
2f6: 1a 2e mov r1, r26
2f8: aa 1b sub r26, r26
2fa: bb 1b sub r27, r27
2fc: fd 01 movw r30, r26
2fe: 0d c0 rjmp .+26 ; 0x31a <__udivmodsi4_ep>
00000300 <__udivmodsi4_loop>:
300: aa 1f adc r26, r26
302: bb 1f adc r27, r27
304: ee 1f adc r30, r30
306: ff 1f adc r31, r31
308: a2 17 cp r26, r18
30a: b3 07 cpc r27, r19
30c: e4 07 cpc r30, r20
30e: f5 07 cpc r31, r21
310: 20 f0 brcs .+8 ; 0x31a <__udivmodsi4_ep>
312: a2 1b sub r26, r18
314: b3 0b sbc r27, r19
316: e4 0b sbc r30, r20
318: f5 0b sbc r31, r21
0000031a <__udivmodsi4_ep>:
31a: 66 1f adc r22, r22
31c: 77 1f adc r23, r23
31e: 88 1f adc r24, r24
320: 99 1f adc r25, r25
322: 1a 94 dec r1
324: 69 f7 brne .-38 ; 0x300 <__udivmodsi4_loop>
326: 60 95 com r22
328: 70 95 com r23
32a: 80 95 com r24
32c: 90 95 com r25
32e: 9b 01 movw r18, r22
330: ac 01 movw r20, r24
332: bd 01 movw r22, r26
334: cf 01 movw r24, r30
336: 08 95 ret
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