/*******************************************************************
 *
 *    DESCRIPTION: UART transmitter module.
 *
 *    AUTHOR: Thomas Oelsner
 *
 *    HISTORY: 10/04/96    
 *
 *******************************************************************/
module txmit (mclkx16, write, reset, tx, txrdy, data);

input    mclkx16;		      	// Input clock, 16 x baudrate clock used for synchronization.
input    write;		      	// Transmit write strobe.
input	   reset;		      	// Global reset.
output   tx;      reg   tx;   // Transmit data output.
		         
output   txrdy;		      	// Transmitter ready to recieve next byte to be send

input    [7:0] data;       	// 8 bit input data bus


reg      write1, write2;      // write signal delayed 1 and 2 cycles.
reg      txdone1;        	   // txdone signal delayed one cycle.


// Transmit shift register bits
reg      [7:0] thr;			   // Transmit hold register
reg      [7:0] tsr;           // Transmit shift register, used for shifting out data to tx.
reg      tag1, tag2;		      // Tag bits for used for detecting, when the tsr are empty.
wire		paritymode = 1'b1; 	// Initializing to 1 = odd parity, 0 = even parity. 
reg      txparity;		   	// Parity generation register.


// Transmit clock and other control signals
reg      txclk;            	// Transmit clock, i.e. baudrate clock = 1/16'th of mclkx16.
wire     txdone;		      	// Set to high, when shifting of byte is done.
wire     paritycycle;	   	// Set to high, one cycle next to last shift cycle.
reg      txdatardy;        	// Set to hign, when data is ready in transmit hold register.
reg      [2:0] cnt;           // Counter used for generating the internal baud rate clock.




// Paritycycle = 1 on next to last cycle, this means when tsr[1] gets tag2.
assign   paritycycle = tsr[1] && !(tag2 || tag1 || tsr[7] || tsr[6] || tsr[5] || tsr[4] || tsr[3] || tsr[2]);



// txdone = 1 when done shifting, this means when tx gets tag2.
assign   txdone = !(tag2 || tag1 || tsr[7] || tsr[6] || tsr[5] || tsr[4] || tsr[3] || tsr[2] || tsr[1] || tsr[0]);



// Ready for new date to be written, when no data is in transmit hold register.
assign    txrdy = !txdatardy;



//Latch data[7:0] into the transmit hold register at posedge of write.
	always @(write or data)
   if (~write) 
   		  thr = data; 



// Toggle txclk every 8 counts, which divides the clock by 16, to generate the baud clock
always @(posedge mclkx16 or posedge reset)
if (reset)
	begin
	txclk <= 1'b0;
	cnt <= 3'b000;
	end
else
	begin
	if (cnt == 3'b000)  
	    txclk <= !txclk; 
	cnt <= cnt + 1;
   end


task idle_reset;
	begin                   		// Apply pseudo Idle state, equal to end of transmission.
		tsr      <= 8'h00;	   	// Reset transmit shift register.
		tag2     <= 1'b0;	      	// Reset tag bit. 
		tag1     <= 1'b0;	      	// Reset tag bit.
//		txparity <= paritymode; 	// Set parity mode for even or odd parity.
		txparity <= 1'b0;				// Reset txparty bit.
		tx       <= 1'b1;	      	// At pseudo idle set Start bit high.
	end
endtask //


task load_data;
	begin                     		// Initialize registers and load next byte of data.
	    tsr        <= thr;	      // Load tsr from thr.
	    tag2       <= 1'b1;	      // Set tag bits for detecting when shifting is done. 
	    tag1       <= 1'b1;	      // Set tag bits for detecting when shifting is done.
	    txparity   <= paritymode;	// Set parity mode bit, 0 = even parity, 1 = odd parity
	    tx         <= 1'b0;	      // Set start bit low.
   end
endtask //


task shift_data;
	begin
		tsr     <= tsr >> 1;      		 // Right shift tsr by one.
   	tsr[7]  <= tag1;          		 // Set tsr[7] = tag1.   
   	tag1    <= tag2;          		 // Set tag1 = tag2.
   	tag2    <= 1'b0;          		 // Set tag2 = 0. 
	   txparity <= txparity ^ tsr[0]; // Generate parity.
	end
endtask //


// Shifting out data to tx.
always @(posedge txclk or posedge reset)
if (reset)
	idle_reset;						// Reset internal bits of transmitter.
else
	begin
		if (txdone && txdatardy)
			load_data;				// Load new data to tsr.
		else
	   	begin   
			shift_data;				// Shift contents of tsr to tx output.	
         
	    	// Shift out data or parity bit or stop/idle bit.
	     	if (txdone )
		   	tx <= 1'b1;	     		// Output stop/idle bit.
	    	else if (paritycycle)
		   	tx <= txparity;   	// Output parity bit.
	     	else
				tx <= tsr[0];     	//Shift out data bit.
	    	end
	end


always @(posedge mclkx16 or posedge reset)
if (reset) 
	begin
	txdatardy <= 1'b0;
	write2 <= 1'b1;
	write1 <= 1'b1;		
	txdone1 <= 1'b1;		            // Set equal to txdone at reset.
	end
else
	begin
	if (write1 &&  !write2)
	   txdatardy  <= 1'b1;           // At risign edge of write, new data are latched in thr, and txdatardy are set.

	else if (!txdone &&  txdone1)
	     	txdatardy  <= 1'b0;			// At falling edge of txdone, the thr has been loaded into tsr, so txdatardy are reset.

	// Generate delayed versions of write and txdone signals for edge detection.
	write2 <= write1;
	write1 <= write;
	txdone1 <= txdone;
	end 

endmodule