Version 1.1 - Preliminary
5/8/97
Fixed active low read bug in VHDL model
Modified design to synthesize without warnings

Version 1.2
6/9/97
Added VHDL Test Bench
Enhanced documentation
Improvements to Verilog Test Bench to allow slower
  speed grade parts in post-layout simulation.

Version 1.3
7/22/97
Renamed RXMIT.VHD to RXCVER.VHD to match filenames 
with the Verilog version.
Uncommented the latches in RXCVER.VHD and TXMIT.VHD
to ensure correct Silos III post-layout simulation,
and maintain Synopsys VHDL synthesis compatibility.
This will result in warnings about latchs during synthesis
in Synplify-Lite. But it's neccessary for proper operation.