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;============================================================================*
* File name :   ADC.asm                                                      *
* Description : PROGRAM TO INITIALIZE THE ADC MODULE OF 240x                 *
* This program initializes the ADC module of the '240x and does a conversion *
* of all the analog input channels. The results of the conversion are        *
* available in the RESULTSn register, which can be accessed by the user      *
* application. The ADC operates as one 16-state sequencer & the conversions  *
* are stopped once the sequencer reaches EOS (End of sequence)               *
;============================================================================*

                .title   "ADC" 

                .bss     GPR0,1             ; General purpose register
                .include 240x.h
                .def	 _c_int0

            .sect  "vectors"

RSVECT      B    _c_int0            ; Reset Vector
INT1        B    GISR1            ; Interrupt Level 1
INT2        B    GISR2            ; Interrupt Level 2
INT3        B    GISR3            ; Interrupt Level 3
INT4        B    GISR4            ; Interrupt Level 4
INT5        B    GISR5            ; Interrupt Level 5
INT6        B    GISR6            ; Interrupt Level 6
RESERVED    B    PHANTOM          ; Reserved
SW_INT8     B    PHANTOM          ; Software Interrupt
SW_INT9     B    PHANTOM          ; Software Interrupt
SW_INT10    B    PHANTOM          ; Software Interrupt
SW_INT11    B    PHANTOM          ; Software Interrupt
SW_INT12    B    PHANTOM          ; Software Interrupt
SW_INT13    B    PHANTOM          ; Software Interrupt
SW_INT14    B    PHANTOM          ; Software Interrupt
SW_INT15    B    PHANTOM          ; Software Interrupt
SW_INT16    B    PHANTOM          ; Software Interrupt
TRAP        B    PHANTOM          ; Trap vector
NMI         B    NMI              ; Non-maskable Interrupt
EMU_TRAP    B    PHANTOM          ; Emulator Trap
SW_INT20    B    PHANTOM          ; Software Interrupt
SW_INT21    B    PHANTOM          ; Software Interrupt
SW_INT22    B    PHANTOM          ; Software Interrupt
SW_INT23    B    PHANTOM          ; Software Interrupt
SW_INT24    B    PHANTOM          ; Software Interrupt
SW_INT25    B    PHANTOM          ; Software Interrupt
SW_INT26    B    PHANTOM          ; Software Interrupt
SW_INT27    B    PHANTOM          ; Software Interrupt
SW_INT28    B    PHANTOM          ; Software Interrupt
SW_INT29    B    PHANTOM          ; Software Interrupt
SW_INT30    B    PHANTOM          ; Software Interrupt
SW_INT31    B    PHANTOM          ; Software Interrupt



;-------------------------------------------------------------
; M A C R O - Definitions
;-------------------------------------------------------------
KICK_DOG        .macro                      ; Watchdog reset macro
                LDP      #00E0h             ; DP-->7000h-707Fh
                SPLK     #05555h, WDKEY
                SPLK     #0AAAAh, WDKEY
                LDP      #0h                ; DP-->0000h-007Fh
                .endm

                .text                   
_c_int0:        LDP      #0h                ; Set DP=0
                SETC     INTM               ; Disable interrupts
                CLRC     SXM
                SPLK     #0000h,IMR         ; Mask all core interrupts
                LACC     IFR                ; Read Interrupt flags
                SACL     IFR                ; Clear all interrupt flags
                LDP      #00E0h             ; (E0=224)(E0*80=7000)
                SPLK     #006Fh, WDCR       ; Disable WD 
                SPLK     #0080h,SCSR1       ; Enable clock to ADC module
                KICK_DOG 
                SPLK     #0h,GPR0           ; Set wait state generator for:
                OUT      GPR0,WSGR    
* Initialize ADC registers

                LDP      #0E1h
                SPLK     #0100000000000000b,ADCTRL1 ; Reset ADC module
                SPLK     #0011000000010000b,ADCTRL1 ; Take ADC out of reset
                        ; ||||||||||||||||
                        ; 5432109876543210
                        ; 15 - RSVD | 14 - Reset(1) | 13,12 - Soft & Free
                        ; 11,10,9,8 - Acq.prescalers | 7 - Clock prescaler
                        ; 6 - Cont.run (1) | 5 - Int.priority (Hi.0)
                        ; 4 - Seq.casc (0-dual)
 
* Setup a maximum of 16 conversions

                      SPLK     #15, MAXCONV       ; Setup for 16 conversions

* Program the conversion sequence. This is the sequence of channels that will
* be used for the 16 conversions.

                SPLK     #03210h, CHSELSEQ1 ; Convert Channels 0,1,2,3
                SPLK     #07654h, CHSELSEQ2 ; Convert Channels 4,5,6,7
                SPLK     #0BA98h, CHSELSEQ3 ; Convert Channels 8,9,10,11
                SPLK     #0FEDCh, CHSELSEQ4 ; Convert Channels 12,13,14,15

                SPLK     #0010000000000000b,ADCTRL2 ; Start the conversions
                        ; ||||||||||||||||
                        ; 5432109876543210
CHK_EOS1:       BIT      ADCTRL2, BIT12     ; Wait for SEQ1 Busy bit to 
                                            ; clear
                BCND     CHK_EOS1, TC       ; If TC=1, keep looping.

                

                RPT      #8
                NOP
                LACC     RESULT0
                SACL     AR0
                               
LOOP:           LDP      #0
                LACC     GPR0
                
                BCND     NEXT,GT
                SPLK     #00FFH,GPR0         ; Set wait state generator for:
NEXT            NOP
                OUT      GPR0,0300H 
                RPT      #255
                NOP
                LACC     GPR0
                SUB      #1
                SACL     GPR0 
                
                
                
                B        LOOP               ; The conversion results are now
                                            ; available in the RESULTSn regs.
GISR1:          RET
GISR2:          RET
GISR3:          RET
GISR4:          RET
GISR5:          RET
GISR6:          RET
PHANTOM:        RET
                .end