Release 6.3i Par G.38Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.WANHQ::  Fri Nov 03 16:24:02 2006D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 szz_map.ncd szz.ncd
szz.pcf Constraints file: szz.pcfLoading device database for application Par from file "szz_map.ncd".   "szz" is an NCD, version 2.38, device xc3s200, package pq208, speed -4Loading device for application Par from file '3s200.nph' in environment
D:/Xilinx.Device speed data version:  PRODUCTION 1.35 2004-11-11.Resolved that IOB <dout<0>> must be placed at site P114.Resolved that IOB <dout<1>> must be placed at site P115.Resolved that IOB <dout<2>> must be placed at site P117.Resolved that IOB <dout<3>> must be placed at site P119.Resolved that IOB <dout<4>> must be placed at site P120.Resolved that IOB <dout<5>> must be placed at site P113.Resolved that IOB <dout<6>> must be placed at site P111.Resolved that IOB <dout<7>> must be placed at site P116.Resolved that IOB <EN> must be placed at site P108.Resolved that IOB <speak> must be placed at site P162.Resolved that IOB <selout<0>> must be placed at site P106.Resolved that IOB <selout<1>> must be placed at site P101.Resolved that IOB <selout<2>> must be placed at site P100.Resolved that IOB <selout<3>> must be placed at site P97.Resolved that IOB <md1> must be placed at site P94.Resolved that IOB <md3> must be placed at site P87.Resolved that IOB <md2<0>> must be placed at site P93.Resolved that IOB <md2<1>> must be placed at site P90.Device utilization summary:   Number of External IOBs            19 out of 141    13%      Number of LOCed External IOBs   18 out of 19     94%   Number of Slices                  186 out of 1920    9%   Number of BUFGMUXs                  1 out of 8      12%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:989903) REAL time: 2 secs Phase 3.8.....Phase 3.8 (Checksum:99e4d5) REAL time: 2 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.18Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs Writing design to file szz.ncd.Total REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 1 secs Phase 1: 1182 unrouted;       REAL time: 2 secs Phase 2: 1101 unrouted;       REAL time: 2 secs Phase 3: 379 unrouted;       REAL time: 2 secs Phase 4: 0 unrouted;       REAL time: 3 secs Total REAL time to Router completion: 3 secs Total CPU time to Router completion: 1 secs Generating "par" statistics.**************************Generating Clock Report**************************+-------------------------+----------+------+------+------------+-------------+|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+-------------------------+----------+------+------+------------+-------------+|       inclk_BUFGP       |  BUFGMUX1| No   |   51 |  0.004     |  1.014      |+-------------------------+----------+------+------+------------+-------------+|            _n0054       |   Local  |      |   12 |  1.734     |  2.523      |+-------------------------+----------+------+------+------------+-------------+|              clk1       |   Local  |      |    4 |  1.423     |  3.262      |+-------------------------+----------+------+------+------------+-------------+|               clk       |   Local  |      |   21 |  0.117     |  2.724      |+-------------------------+----------+------+------+------------+-------------+   The Delay Summary Report   The SCORE FOR THIS DESIGN is: 133The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        0.833   The MAXIMUM PIN DELAY IS:                               3.262   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.500   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------         813         314          53           2           0           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 3 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage:  62 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file szz.ncd.PAR done.