sys_sigaltstack_glue:        la      %r4,SP_PTREGS(%r15)   # load pt_regs as parameter        jg      sys_sigaltstack       # branch to sys_sigreturn#ifdef CONFIG_S390_SUPPORTsys32_sigaltstack_glue:        la      %r4,SP_PTREGS(%r15)   # load pt_regs as parameter        jg      sys32_sigaltstack_wrapper # branch to sys_sigreturn#endif/* * Program check handler routine */        .globl  pgm_check_handlerpgm_check_handler:/* * First we need to check for a special case: * Single stepping an instruction that disables the PER event mask will * cause a PER event AFTER the mask has been set. Example: SVC or LPSW. * For a single stepped SVC the program check handler gets control after * the SVC new PSW has been loaded. But we want to execute the SVC first and * then handle the PER event. Therefore we update the SVC old PSW to point * to the pgm_check_handler and branch to the SVC handler after we checked * if we have to load the kernel stack register. * For every other possible cause for PER event without the PER mask set * we just ignore the PER event (FIXME: is there anything we have to do * for LPSW?). */	STORE_TIMER __LC_SYNC_ENTER_TIMER	SAVE_ALL_BASE __LC_SAVE_AREA        tm      __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception        jnz     pgm_per                  # got per exception -> special case	SAVE_ALL __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1#ifdef CONFIG_VIRT_CPU_ACCOUNTING	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	jz	pgm_no_vtime	UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMERpgm_no_vtime:#endif	lg	%r9,__LC_THREAD_INFO	# load pointer to thread_info struct	lgf     %r3,__LC_PGM_ILC	 # load program interruption code	lghi	%r8,0x7f	ngr	%r8,%r3pgm_do_call:        sll     %r8,3        larl    %r1,pgm_check_table        lg      %r1,0(%r8,%r1)		 # load address of handler routine        la      %r2,SP_PTREGS(%r15)	 # address of register-save area	larl	%r14,sysc_return        br      %r1			 # branch to interrupt-handler## handle per exception#pgm_per:        tm      __LC_PGM_OLD_PSW,0x40    # test if per event recording is on        jnz     pgm_per_std              # ok, normal per event from user space# ok its one of the special cases, now we need to find out which one        clc     __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW        je      pgm_svcper# no interesting special case, ignore PER event	lmg	%r12,%r15,__LC_SAVE_AREA	lpswe   __LC_PGM_OLD_PSW## Normal per exception#pgm_per_std:	SAVE_ALL __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1#ifdef CONFIG_VIRT_CPU_ACCOUNTING	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	jz	pgm_no_vtime2	UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMERpgm_no_vtime2:#endif	lg	%r9,__LC_THREAD_INFO	# load pointer to thread_info struct	lg	%r1,__TI_task(%r9)	mvc	__THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID	mvc	__THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS	mvc	__THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID	oi	__TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP	lgf     %r3,__LC_PGM_ILC	 # load program interruption code	lghi	%r8,0x7f	ngr	%r8,%r3			 # clear per-event-bit and ilc	je	sysc_return	j	pgm_do_call## it was a single stepped SVC that is causing all the trouble#pgm_svcper:	SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1#ifdef CONFIG_VIRT_CPU_ACCOUNTING	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	jz	pgm_no_vtime3	UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMERpgm_no_vtime3:#endif	llgh    %r7,__LC_SVC_INT_CODE	# get svc number from lowcore	lg	%r9,__LC_THREAD_INFO	# load pointer to thread_info struct	lg	%r1,__TI_task(%r9)	mvc	__THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID	mvc	__THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS	mvc	__THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID	oi	__TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP	stosm	__SF_EMPTY(%r15),0x03	# reenable interrupts	j	sysc_do_svc/* * IO interrupt handler routine */        .globl io_int_handlerio_int_handler:	STORE_TIMER __LC_ASYNC_ENTER_TIMER	stck	__LC_INT_CLOCK	SAVE_ALL_BASE __LC_SAVE_AREA+32        SAVE_ALL __LC_IO_OLD_PSW,__LC_SAVE_AREA+32,0#ifdef CONFIG_VIRT_CPU_ACCOUNTING	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	jz	io_no_vtime	UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMERio_no_vtime:#endif	lg	%r9,__LC_THREAD_INFO	# load pointer to thread_info struct        la      %r2,SP_PTREGS(%r15)    # address of register-save area	brasl   %r14,do_IRQ            # call standard irq handlerio_return:        tm      SP_PSW+1(%r15),0x01    # returning to user ?#ifdef CONFIG_PREEMPT	jno     io_preempt             # no -> check for preemptive scheduling#else        jno     io_leave               # no-> skip resched & signal#endif	tm	__TI_flags+7(%r9),_TIF_WORK_INT	jnz	io_work                # there is work to do (signals etc.)io_leave:        RESTORE_ALL 0#ifdef CONFIG_PREEMPTio_preempt:	icm	%r0,15,__TI_precount(%r9)		jnz     io_leave	# switch to kernel stack	lg	%r1,SP_R15(%r15)	aghi	%r1,-SP_SIZE	mvc	SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)        xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain	lgr	%r15,%r1io_resume_loop:	tm	__TI_flags+7(%r9),_TIF_NEED_RESCHED	jno	io_leave	larl    %r1,.Lc_pactive	mvc     __TI_precount(4,%r9),0(%r1)        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts	brasl   %r14,schedule          # call schedule        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts	xc      __TI_precount(4,%r9),__TI_precount(%r9)	j	io_resume_loop#endif## switch to kernel stack, then check TIF bits#io_work:	lg	%r1,__LC_KERNEL_STACK	aghi	%r1,-SP_SIZE	mvc	SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)        xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain	lgr	%r15,%r1## One of the work bits is on. Find out which one.# Checked are: _TIF_SIGPENDING and _TIF_NEED_RESCHED#io_work_loop:	tm	__TI_flags+7(%r9),_TIF_NEED_RESCHED	jo	io_reschedule	tm	__TI_flags+7(%r9),_TIF_SIGPENDING	jo	io_sigpending	j	io_leave## _TIF_NEED_RESCHED is set, call schedule#	io_reschedule:        	stosm   __SF_EMPTY(%r15),0x03	# reenable interrupts	brasl   %r14,schedule		# call scheduler	stnsm   __SF_EMPTY(%r15),0xfc	# disable I/O and ext. interrupts	tm	__TI_flags+7(%r9),_TIF_WORK_INT	jz	io_leave		# there is no work to do	j	io_work_loop## _TIF_SIGPENDING is set, call do_signal#io_sigpending:     	stosm   __SF_EMPTY(%r15),0x03	# reenable interrupts	la      %r2,SP_PTREGS(%r15)	# load pt_regs	slgr    %r3,%r3			# clear *oldset	brasl	%r14,do_signal		# call do_signal	stnsm   __SF_EMPTY(%r15),0xfc	# disable I/O and ext. interrupts	j	sysc_leave		# out of here, do NOT recheck/* * External interrupt handler routine */        .globl  ext_int_handlerext_int_handler:	STORE_TIMER __LC_ASYNC_ENTER_TIMER	stck	__LC_INT_CLOCK	SAVE_ALL_BASE __LC_SAVE_AREA+32        SAVE_ALL __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32,0#ifdef CONFIG_VIRT_CPU_ACCOUNTING	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	jz	ext_no_vtime	UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMERext_no_vtime:#endif	lg	%r9,__LC_THREAD_INFO	# load pointer to thread_info struct	la	%r2,SP_PTREGS(%r15)    # address of register-save area	llgh	%r3,__LC_EXT_INT_CODE  # get interruption code	brasl   %r14,do_extint	j	io_return/* * Machine check handler routines */        .globl mcck_int_handlermcck_int_handler:	STORE_TIMER __LC_ASYNC_ENTER_TIMER	SAVE_ALL_BASE __LC_SAVE_AREA+64        SAVE_ALL __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64,0#ifdef CONFIG_VIRT_CPU_ACCOUNTING	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	jz	mcck_no_vtime	UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMERmcck_no_vtime:#endif	brasl   %r14,s390_do_machine_checkmcck_return:        RESTORE_ALL 0#ifdef CONFIG_SMP/* * Restart interruption handler, kick starter for additional CPUs */        .globl restart_int_handlerrestart_int_handler:        lg      %r15,__LC_SAVE_AREA+120 # load ksp        lghi    %r10,__LC_CREGS_SAVE_AREA        lctlg   %c0,%c15,0(%r10) # get new ctl regs        lghi    %r10,__LC_AREGS_SAVE_AREA        lam     %a0,%a15,0(%r10)        lmg     %r6,%r15,__SF_GPRS(%r15) # load registers from clone        stosm   __SF_EMPTY(%r15),0x04    # now we can turn dat on	jg      start_secondary#else/* * If we do not run with SMP enabled, let the new CPU crash ... */        .globl restart_int_handlerrestart_int_handler:        basr    %r1,0restart_base:        lpswe   restart_crash-restart_base(%r1)        .align 8restart_crash:        .long  0x000a0000,0x00000000,0x00000000,0x00000000restart_go:#endif#ifdef CONFIG_CHECK_STACK/* * The synchronous or the asynchronous stack overflowed. We are dead. * No need to properly save the registers, we are going to panic anyway. * Setup a pt_regs so that show_trace can provide a good call trace. */stack_overflow:	lg	%r15,__LC_PANIC_STACK	# change to panic stack	aghi	%r1,-SP_SIZE	mvc	SP_PSW(16,%r15),0(%r12)	# move user PSW to stack	stmg	%r0,%r11,SP_R0(%r15)	# store gprs %r0-%r11 to kernel stack	la	%r1,__LC_SAVE_AREA	chi	%r12,__LC_SVC_OLD_PSW	je	0f	chi	%r12,__LC_PGM_OLD_PSW	je	0f	la	%r1,__LC_SAVE_AREA+160:	mvc	SP_R12(32,%r15),0(%r1)  # move %r12-%r15 to stack        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain        la      %r2,SP_PTREGS(%r15)	# load pt_regs	jg	kernel_stack_overflow#endifcleanup_table_system_call:	.quad	system_call, sysc_do_svccleanup_table_sysc_return:	.quad	sysc_return, sysc_leavecleanup_table_sysc_leave:	.quad	sysc_leave, sysc_work_loopcleanup_table_sysc_work_loop:	.quad	sysc_work_loop, sysc_reschedulecleanup_critical:	clc	8(8,%r12),BASED(cleanup_table_system_call)	jl	0f	clc	8(8,%r12),BASED(cleanup_table_system_call+8)	jl	cleanup_system_call0:	clc	8(8,%r12),BASED(cleanup_table_sysc_return)	jl	0f	clc	8(8,%r12),BASED(cleanup_table_sysc_return+8)	jl	cleanup_sysc_return0:	clc	8(8,%r12),BASED(cleanup_table_sysc_leave)	jl	0f	clc	8(8,%r12),BASED(cleanup_table_sysc_leave+8)	jl	cleanup_sysc_leave0:	clc	8(8,%r12),BASED(cleanup_table_sysc_work_loop)	jl	0f	clc	8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)	jl	cleanup_sysc_leave0:	br	%r14cleanup_system_call:	mvc	__LC_RETURN_PSW(16),0(%r12)#ifdef CONFIG_VIRT_CPU_ACCOUNTING	clc	__LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)	jh	0f	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER0:	clc	__LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)	jhe	cleanup_vtime#endif	clc	__LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)	jh	0f	mvc	__LC_SAVE_AREA(32),__LC_SAVE_AREA+320:	stg	%r13,__LC_SAVE_AREA+40	SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1	stg	%r15,__LC_SAVE_AREA+56	llgh	%r7,__LC_SVC_INT_CODE#ifdef CONFIG_VIRT_CPU_ACCOUNTINGcleanup_vtime:	clc	__LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)	jhe	cleanup_stime	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	jz	cleanup_novtime	UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMERcleanup_stime:	clc	__LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)	jh	cleanup_update	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMERcleanup_update:	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMERcleanup_novtime:#endif	mvc	__LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)	la	%r12,__LC_RETURN_PSW	br	%r14cleanup_system_call_insn:	.quad	sysc_saveall#ifdef CONFIG_VIRT_CPU_ACCOUNTING	.quad   system_call	.quad   sysc_vtime	.quad   sysc_stime	.quad   sysc_update#endifcleanup_sysc_return:	mvc	__LC_RETURN_PSW(8),0(%r12)	mvc	__LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)	la	%r12,__LC_RETURN_PSW	br	%r14cleanup_sysc_leave:	clc	8(8,%r12),BASED(cleanup_sysc_leave_insn)	je	0f#ifdef CONFIG_VIRT_CPU_ACCOUNTING	mvc	__LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER	clc	8(8,%r12),BASED(cleanup_sysc_leave_insn+8)	je	0f#endif	mvc	__LC_RETURN_PSW(16),SP_PSW(%r15)	mvc	__LC_SAVE_AREA+32(32),SP_R12(%r15)	lmg	%r0,%r11,SP_R0(%r15)	lg	%r15,SP_R15(%r15)0:	la	%r12,__LC_RETURN_PSW	br	%r14cleanup_sysc_leave_insn:#ifdef CONFIG_VIRT_CPU_ACCOUNTING	.quad	sysc_leave + 16#endif	.quad	sysc_leave + 12/* * Integer constants */               .align 4.Lconst:.Lc_pactive:   .long  PREEMPT_ACTIVE.Lnr_syscalls: .long  NR_syscalls.L0x0130:      .short 0x130.L0x0140:      .short 0x140.L0x0150:      .short 0x150.L0x0160:      .short 0x160.L0x0170:      .short 0x170.Lcritical_start:               .quad  __critical_start.Lcritical_end:               .quad  __critical_end#define SYSCALL(esa,esame,emu)	.long esame	.globl  sys_call_tablesys_call_table:#include "syscalls.S"#undef SYSCALL#ifdef CONFIG_S390_SUPPORT#define SYSCALL(esa,esame,emu)	.long emu	.globl  sys_call_table_emusys_call_table_emu:#include "syscalls.S"#undef SYSCALL#endif