; Perform Register Retiming                          ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion -- Logic Duplication          ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error       ; On                       ;
; Release clears before tri-states             ; Off                      ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/highflu documents/quartwork/singt/singt.fit.eqn.


+----------------+
; Floorplan View ;
+----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/highflu documents/quartwork/singt/singt.pin.


+-----------------------------------------------------------+
; Fitter Resource Usage Summary                             ;
+--------------------------------+--------------------------+
; Resource                       ; Usage                    ;
+--------------------------------+--------------------------+
; Logic cells                    ; 399 / 12,060 ( 3 % )     ;
; Registers                      ; 299 / 12,567 ( 2 % )     ;
; Total LABs                     ; 56 / 1,206 ( 4 % )       ;
; Logic elements in carry chains ; 70                       ;
; User inserted logic cells      ; 0                        ;
; Virtual pins                   ; 0                        ;
; I/O pins                       ; 9 / 173 ( 5 % )          ;
;     -- Clock pins              ; 1 / 2 ( 50 % )           ;
; Global signals                 ; 8                        ;
; M4Ks                           ; 3 / 52 ( 5 % )           ;
; Total memory bits              ; 8,704 / 239,616 ( 3 % )  ;
; Total RAM block bits           ; 13,824 / 239,616 ( 5 % ) ;
; Global clocks                  ; 8 / 8 ( 100 % )          ;
; Maximum fan-out node           ; altera_internal_jtag~TDO ;
; Maximum fan-out                ; 221                      ;
; Total fan-out                  ; 1882                     ;
; Average fan-out                ; 4.50                     ;
+--------------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; CLK  ; 28    ; 1        ; 0            ; 15           ; 2           ; 91                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                        ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+
; DOUT[0] ; 21    ; 1        ; 0            ; 20           ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; DOUT[1] ; 41    ; 1        ; 0            ; 7            ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; DOUT[2] ; 128   ; 3        ; 53           ; 3            ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; DOUT[3] ; 132   ; 3        ; 53           ; 4            ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; DOUT[4] ; 133   ; 3        ; 53           ; 4            ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; DOUT[5] ; 134   ; 3        ; 53           ; 5            ; 2           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; DOUT[6] ; 135   ; 3        ; 53           ; 5            ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; DOUT[7] ; 136   ; 3        ; 53           ; 5            ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+


+-----------------------------------------------------------+
; I/O Bank Usage                                            ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ;
+----------+-----------------+---------------+--------------+
; 1        ; 5 / 44 ( 11 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 42 ( 0 % )  ; 3.3V          ; --           ;