--NB1_q_a[7] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[7]_PORT_A_data_in = VCC;
NB1_q_a[7]_PORT_A_data_in_reg = DFFE(NB1_q_a[7]_PORT_A_data_in, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_data_in = PB1_ram_rom_data_reg[7];
NB1_q_a[7]_PORT_B_data_in_reg = DFFE(NB1_q_a[7]_PORT_B_data_in, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_a[7]_PORT_A_address_reg = DFFE(NB1_q_a[7]_PORT_A_address, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_a[7]_PORT_B_address_reg = DFFE(NB1_q_a[7]_PORT_B_address, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_write_enable = GND;
NB1_q_a[7]_PORT_A_write_enable_reg = DFFE(NB1_q_a[7]_PORT_A_write_enable, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_write_enable = PB1L92;
NB1_q_a[7]_PORT_B_write_enable_reg = DFFE(NB1_q_a[7]_PORT_B_write_enable, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_clock_0 = CLK;
NB1_q_a[7]_clock_1 = A1L5;
NB1_q_a[7]_PORT_A_data_out = MEMORY(NB1_q_a[7]_PORT_A_data_in_reg, NB1_q_a[7]_PORT_B_data_in_reg, NB1_q_a[7]_PORT_A_address_reg, NB1_q_a[7]_PORT_B_address_reg, NB1_q_a[7]_PORT_A_write_enable_reg, NB1_q_a[7]_PORT_B_write_enable_reg, , , NB1_q_a[7]_clock_0, NB1_q_a[7]_clock_1, , , , );
NB1_q_a[7] = NB1_q_a[7]_PORT_A_data_out[0];

--NB1_q_b[7] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[7]
NB1_q_b[7]_PORT_A_data_in = VCC;
NB1_q_b[7]_PORT_A_data_in_reg = DFFE(NB1_q_b[7]_PORT_A_data_in, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_data_in = PB1_ram_rom_data_reg[7];
NB1_q_b[7]_PORT_B_data_in_reg = DFFE(NB1_q_b[7]_PORT_B_data_in, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[7]_PORT_A_address_reg = DFFE(NB1_q_b[7]_PORT_A_address, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = GND;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L92;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = CLK;
NB1_q_b[7]_clock_1 = A1L5;
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[7] = NB1_q_b[7]_PORT_B_data_out[0];


--NB1_q_a[6] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[6]_PORT_A_data_in = VCC;
NB1_q_a[6]_PORT_A_data_in_reg = DFFE(NB1_q_a[6]_PORT_A_data_in, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_data_in = PB1_ram_rom_data_reg[6];
NB1_q_a[6]_PORT_B_data_in_reg = DFFE(NB1_q_a[6]_PORT_B_data_in, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_a[6]_PORT_A_address_reg = DFFE(NB1_q_a[6]_PORT_A_address, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_a[6]_PORT_B_address_reg = DFFE(NB1_q_a[6]_PORT_B_address, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_write_enable = GND;
NB1_q_a[6]_PORT_A_write_enable_reg = DFFE(NB1_q_a[6]_PORT_A_write_enable, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_write_enable = PB1L92;
NB1_q_a[6]_PORT_B_write_enable_reg = DFFE(NB1_q_a[6]_PORT_B_write_enable, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_clock_0 = CLK;
NB1_q_a[6]_clock_1 = A1L5;
NB1_q_a[6]_PORT_A_data_out = MEMORY(NB1_q_a[6]_PORT_A_data_in_reg, NB1_q_a[6]_PORT_B_data_in_reg, NB1_q_a[6]_PORT_A_address_reg, NB1_q_a[6]_PORT_B_address_reg, NB1_q_a[6]_PORT_A_write_enable_reg, NB1_q_a[6]_PORT_B_write_enable_reg, , , NB1_q_a[6]_clock_0, NB1_q_a[6]_clock_1, , , , );
NB1_q_a[6] = NB1_q_a[6]_PORT_A_data_out[0];

--NB1_q_b[6] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[6]
NB1_q_b[6]_PORT_A_data_in = VCC;
NB1_q_b[6]_PORT_A_data_in_reg = DFFE(NB1_q_b[6]_PORT_A_data_in, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_data_in = PB1_ram_rom_data_reg[6];
NB1_q_b[6]_PORT_B_data_in_reg = DFFE(NB1_q_b[6]_PORT_B_data_in, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[6]_PORT_A_address_reg = DFFE(NB1_q_b[6]_PORT_A_address, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[6]_PORT_B_address_reg = DFFE(NB1_q_b[6]_PORT_B_address, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_write_enable = GND;
NB1_q_b[6]_PORT_A_write_enable_reg = DFFE(NB1_q_b[6]_PORT_A_write_enable, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_write_enable = PB1L92;
NB1_q_b[6]_PORT_B_write_enable_reg = DFFE(NB1_q_b[6]_PORT_B_write_enable, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_clock_0 = CLK;
NB1_q_b[6]_clock_1 = A1L5;
NB1_q_b[6]_PORT_B_data_out = MEMORY(NB1_q_b[6]_PORT_A_data_in_reg, NB1_q_b[6]_PORT_B_data_in_reg, NB1_q_b[6]_PORT_A_address_reg, NB1_q_b[6]_PORT_B_address_reg, NB1_q_b[6]_PORT_A_write_enable_reg, NB1_q_b[6]_PORT_B_write_enable_reg, , , NB1_q_b[6]_clock_0, NB1_q_b[6]_clock_1, , , , );
NB1_q_b[6] = NB1_q_b[6]_PORT_B_data_out[0];


--NB1_q_a[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[5]_PORT_A_data_in = VCC;
NB1_q_a[5]_PORT_A_data_in_reg = DFFE(NB1_q_a[5]_PORT_A_data_in, NB1_q_a[5]_clock_0, , , );
NB1_q_a[5]_PORT_B_data_in = PB1_ram_rom_data_reg[5];
NB1_q_a[5]_PORT_B_data_in_reg = DFFE(NB1_q_a[5]_PORT_B_data_in, NB1_q_a[5]_clock_1, , , );
NB1_q_a[5]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_a[5]_PORT_A_address_reg = DFFE(NB1_q_a[5]_PORT_A_address, NB1_q_a[5]_clock_0, , , );
NB1_q_a[5]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_a[5]_PORT_B_address_reg = DFFE(NB1_q_a[5]_PORT_B_address, NB1_q_a[5]_clock_1, , , );
NB1_q_a[5]_PORT_A_write_enable = GND;
NB1_q_a[5]_PORT_A_write_enable_reg = DFFE(NB1_q_a[5]_PORT_A_write_enable, NB1_q_a[5]_clock_0, , , );
NB1_q_a[5]_PORT_B_write_enable = PB1L92;
NB1_q_a[5]_PORT_B_write_enable_reg = DFFE(NB1_q_a[5]_PORT_B_write_enable, NB1_q_a[5]_clock_1, , , );
NB1_q_a[5]_clock_0 = CLK;
NB1_q_a[5]_clock_1 = A1L5;
NB1_q_a[5]_PORT_A_data_out = MEMORY(NB1_q_a[5]_PORT_A_data_in_reg, NB1_q_a[5]_PORT_B_data_in_reg, NB1_q_a[5]_PORT_A_address_reg, NB1_q_a[5]_PORT_B_address_reg, NB1_q_a[5]_PORT_A_write_enable_reg, NB1_q_a[5]_PORT_B_write_enable_reg, , , NB1_q_a[5]_clock_0, NB1_q_a[5]_clock_1, , , , );
NB1_q_a[5] = NB1_q_a[5]_PORT_A_data_out[0];

--NB1_q_b[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[5]
NB1_q_b[5]_PORT_A_data_in = VCC;
NB1_q_b[5]_PORT_A_data_in_reg = DFFE(NB1_q_b[5]_PORT_A_data_in, NB1_q_b[5]_clock_0, , , );
NB1_q_b[5]_PORT_B_data_in = PB1_ram_rom_data_reg[5];
NB1_q_b[5]_PORT_B_data_in_reg = DFFE(NB1_q_b[5]_PORT_B_data_in, NB1_q_b[5]_clock_1, , , );
NB1_q_b[5]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[5]_PORT_A_address_reg = DFFE(NB1_q_b[5]_PORT_A_address, NB1_q_b[5]_clock_0, , , );
NB1_q_b[5]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[5]_PORT_B_address_reg = DFFE(NB1_q_b[5]_PORT_B_address, NB1_q_b[5]_clock_1, , , );
NB1_q_b[5]_PORT_A_write_enable = GND;
NB1_q_b[5]_PORT_A_write_enable_reg = DFFE(NB1_q_b[5]_PORT_A_write_enable, NB1_q_b[5]_clock_0, , , );
NB1_q_b[5]_PORT_B_write_enable = PB1L92;
NB1_q_b[5]_PORT_B_write_enable_reg = DFFE(NB1_q_b[5]_PORT_B_write_enable, NB1_q_b[5]_clock_1, , , );
NB1_q_b[5]_clock_0 = CLK;
NB1_q_b[5]_clock_1 = A1L5;
NB1_q_b[5]_PORT_B_data_out = MEMORY(NB1_q_b[5]_PORT_A_data_in_reg, NB1_q_b[5]_PORT_B_data_in_reg, NB1_q_b[5]_PORT_A_address_reg, NB1_q_b[5]_PORT_B_address_reg, NB1_q_b[5]_PORT_A_write_enable_reg, NB1_q_b[5]_PORT_B_write_enable_reg, , , NB1_q_b[5]_clock_0, NB1_q_b[5]_clock_1, , , , );
NB1_q_b[5] = NB1_q_b[5]_PORT_B_data_out[0];


--NB1_q_a[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[4]_PORT_A_data_in = VCC;
NB1_q_a[4]_PORT_A_data_in_reg = DFFE(NB1_q_a[4]_PORT_A_data_in, NB1_q_a[4]_clock_0, , , );
NB1_q_a[4]_PORT_B_data_in = PB1_ram_rom_data_reg[4];
NB1_q_a[4]_PORT_B_data_in_reg = DFFE(NB1_q_a[4]_PORT_B_data_in, NB1_q_a[4]_clock_1, , , );
NB1_q_a[4]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_a[4]_PORT_A_address_reg = DFFE(NB1_q_a[4]_PORT_A_address, NB1_q_a[4]_clock_0, , , );
NB1_q_a[4]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_a[4]_PORT_B_address_reg = DFFE(NB1_q_a[4]_PORT_B_address, NB1_q_a[4]_clock_1, , , );
NB1_q_a[4]_PORT_A_write_enable = GND;
NB1_q_a[4]_PORT_A_write_enable_reg = DFFE(NB1_q_a[4]_PORT_A_write_enable, NB1_q_a[4]_clock_0, , , );
NB1_q_a[4]_PORT_B_write_enable = PB1L92;
NB1_q_a[4]_PORT_B_write_enable_reg = DFFE(NB1_q_a[4]_PORT_B_write_enable, NB1_q_a[4]_clock_1, , , );
NB1_q_a[4]_clock_0 = CLK;
NB1_q_a[4]_clock_1 = A1L5;
NB1_q_a[4]_PORT_A_data_out = MEMORY(NB1_q_a[4]_PORT_A_data_in_reg, NB1_q_a[4]_PORT_B_data_in_reg, NB1_q_a[4]_PORT_A_address_reg, NB1_q_a[4]_PORT_B_address_reg, NB1_q_a[4]_PORT_A_write_enable_reg, NB1_q_a[4]_PORT_B_write_enable_reg, , , NB1_q_a[4]_clock_0, NB1_q_a[4]_clock_1, , , , );
NB1_q_a[4] = NB1_q_a[4]_PORT_A_data_out[0];

--NB1_q_b[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[4]
NB1_q_b[4]_PORT_A_data_in = VCC;
NB1_q_b[4]_PORT_A_data_in_reg = DFFE(NB1_q_b[4]_PORT_A_data_in, NB1_q_b[4]_clock_0, , , );
NB1_q_b[4]_PORT_B_data_in = PB1_ram_rom_data_reg[4];
NB1_q_b[4]_PORT_B_data_in_reg = DFFE(NB1_q_b[4]_PORT_B_data_in, NB1_q_b[4]_clock_1, , , );
NB1_q_b[4]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[4]_PORT_A_address_reg = DFFE(NB1_q_b[4]_PORT_A_address, NB1_q_b[4]_clock_0, , , );
NB1_q_b[4]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[4]_PORT_B_address_reg = DFFE(NB1_q_b[4]_PORT_B_address, NB1_q_b[4]_clock_1, , , );
NB1_q_b[4]_PORT_A_write_enable = GND;
NB1_q_b[4]_PORT_A_write_enable_reg = DFFE(NB1_q_b[4]_PORT_A_write_enable, NB1_q_b[4]_clock_0, , , );
NB1_q_b[4]_PORT_B_write_enable = PB1L92;
NB1_q_b[4]_PORT_B_write_enable_reg = DFFE(NB1_q_b[4]_PORT_B_write_enable, NB1_q_b[4]_clock_1, , , );
NB1_q_b[4]_clock_0 = CLK;
NB1_q_b[4]_clock_1 = A1L5;
NB1_q_b[4]_PORT_B_data_out = MEMORY(NB1_q_b[4]_PORT_A_data_in_reg, NB1_q_b[4]_PORT_B_data_in_reg, NB1_q_b[4]_PORT_A_address_reg, NB1_q_b[4]_PORT_B_address_reg, NB1_q_b[4]_PORT_A_write_enable_reg, NB1_q_b[4]_PORT_B_write_enable_reg, , , NB1_q_b[4]_clock_0, NB1_q_b[4]_clock_1, , , , );
NB1_q_b[4] = NB1_q_b[4]_PORT_B_data_out[0];


--NB1_q_a[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[3]_PORT_A_data_in = VCC;
NB1_q_a[3]_PORT_A_data_in_reg = DFFE(NB1_q_a[3]_PORT_A_data_in, NB1_q_a[3]_clock_0, , , );
NB1_q_a[3]_PORT_B_data_in = PB1_ram_rom_data_reg[3];
NB1_q_a[3]_PORT_B_data_in_reg = DFFE(NB1_q_a[3]_PORT_B_data_in, NB1_q_a[3]_clock_1, , , );
NB1_q_a[3]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_a[3]_PORT_A_address_reg = DFFE(NB1_q_a[3]_PORT_A_address, NB1_q_a[3]_clock_0, , , );
NB1_q_a[3]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_a[3]_PORT_B_address_reg = DFFE(NB1_q_a[3]_PORT_B_address, NB1_q_a[3]_clock_1, , , );
NB1_q_a[3]_PORT_A_write_enable = GND;
NB1_q_a[3]_PORT_A_write_enable_reg = DFFE(NB1_q_a[3]_PORT_A_write_enable, NB1_q_a[3]_clock_0, , , );
NB1_q_a[3]_PORT_B_write_enable = PB1L92;
NB1_q_a[3]_PORT_B_write_enable_reg = DFFE(NB1_q_a[3]_PORT_B_write_enable, NB1_q_a[3]_clock_1, , , );
NB1_q_a[3]_clock_0 = CLK;
NB1_q_a[3]_clock_1 = A1L5;
NB1_q_a[3]_PORT_A_data_out = MEMORY(NB1_q_a[3]_PORT_A_data_in_reg, NB1_q_a[3]_PORT_B_data_in_reg, NB1_q_a[3]_PORT_A_address_reg, NB1_q_a[3]_PORT_B_address_reg, NB1_q_a[3]_PORT_A_write_enable_reg, NB1_q_a[3]_PORT_B_write_enable_reg, , , NB1_q_a[3]_clock_0, NB1_q_a[3]_clock_1, , , , );
NB1_q_a[3] = NB1_q_a[3]_PORT_A_data_out[0];

--NB1_q_b[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[3]
NB1_q_b[3]_PORT_A_data_in = VCC;
NB1_q_b[3]_PORT_A_data_in_reg = DFFE(NB1_q_b[3]_PORT_A_data_in, NB1_q_b[3]_clock_0, , , );
NB1_q_b[3]_PORT_B_data_in = PB1_ram_rom_data_reg[3];
NB1_q_b[3]_PORT_B_data_in_reg = DFFE(NB1_q_b[3]_PORT_B_data_in, NB1_q_b[3]_clock_1, , , );
NB1_q_b[3]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[3]_PORT_A_address_reg = DFFE(NB1_q_b[3]_PORT_A_address, NB1_q_b[3]_clock_0, , , );
NB1_q_b[3]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[3]_PORT_B_address_reg = DFFE(NB1_q_b[3]_PORT_B_address, NB1_q_b[3]_clock_1, , , );
NB1_q_b[3]_PORT_A_write_enable = GND;
NB1_q_b[3]_PORT_A_write_enable_reg = DFFE(NB1_q_b[3]_PORT_A_write_enable, NB1_q_b[3]_clock_0, , , );
NB1_q_b[3]_PORT_B_write_enable = PB1L92;
NB1_q_b[3]_PORT_B_write_enable_reg = DFFE(NB1_q_b[3]_PORT_B_write_enable, NB1_q_b[3]_clock_1, , , );
NB1_q_b[3]_clock_0 = CLK;
NB1_q_b[3]_clock_1 = A1L5;
NB1_q_b[3]_PORT_B_data_out = MEMORY(NB1_q_b[3]_PORT_A_data_in_reg, NB1_q_b[3]_PORT_B_data_in_reg, NB1_q_b[3]_PORT_A_address_reg, NB1_q_b[3]_PORT_B_address_reg, NB1_q_b[3]_PORT_A_write_enable_reg, NB1_q_b[3]_PORT_B_write_enable_reg, , , NB1_q_b[3]_clock_0, NB1_q_b[3]_clock_1, , , , );
NB1_q_b[3] = NB1_q_b[3]_PORT_B_data_out[0];


--NB1_q_a[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[2]_PORT_A_data_in = VCC;
NB1_q_a[2]_PORT_A_data_in_reg = DFFE(NB1_q_a[2]_PORT_A_data_in, NB1_q_a[2]_clock_0, , , );
NB1_q_a[2]_PORT_B_data_in = PB1_ram_rom_data_reg[2];
NB1_q_a[2]_PORT_B_data_in_reg = DFFE(NB1_q_a[2]_PORT_B_data_in, NB1_q_a[2]_clock_1, , , );
NB1_q_a[2]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_a[2]_PORT_A_address_reg = DFFE(NB1_q_a[2]_PORT_A_address, NB1_q_a[2]_clock_0, , , );
NB1_q_a[2]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_a[2]_PORT_B_address_reg = DFFE(NB1_q_a[2]_PORT_B_address, NB1_q_a[2]_clock_1, , , );
NB1_q_a[2]_PORT_A_write_enable = GND;
NB1_q_a[2]_PORT_A_write_enable_reg = DFFE(NB1_q_a[2]_PORT_A_write_enable, NB1_q_a[2]_clock_0, , , );
NB1_q_a[2]_PORT_B_write_enable = PB1L92;
NB1_q_a[2]_PORT_B_write_enable_reg = DFFE(NB1_q_a[2]_PORT_B_write_enable, NB1_q_a[2]_clock_1, , , );
NB1_q_a[2]_clock_0 = CLK;
NB1_q_a[2]_clock_1 = A1L5;
NB1_q_a[2]_PORT_A_data_out = MEMORY(NB1_q_a[2]_PORT_A_data_in_reg, NB1_q_a[2]_PORT_B_data_in_reg, NB1_q_a[2]_PORT_A_address_reg, NB1_q_a[2]_PORT_B_address_reg, NB1_q_a[2]_PORT_A_write_enable_reg, NB1_q_a[2]_PORT_B_write_enable_reg, , , NB1_q_a[2]_clock_0, NB1_q_a[2]_clock_1, , , , );
NB1_q_a[2] = NB1_q_a[2]_PORT_A_data_out[0];

--NB1_q_b[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[2]
NB1_q_b[2]_PORT_A_data_in = VCC;
NB1_q_b[2]_PORT_A_data_in_reg = DFFE(NB1_q_b[2]_PORT_A_data_in, NB1_q_b[2]_clock_0, , , );
NB1_q_b[2]_PORT_B_data_in = PB1_ram_rom_data_reg[2];
NB1_q_b[2]_PORT_B_data_in_reg = DFFE(NB1_q_b[2]_PORT_B_data_in, NB1_q_b[2]_clock_1, , , );
NB1_q_b[2]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[2]_PORT_A_address_reg = DFFE(NB1_q_b[2]_PORT_A_address, NB1_q_b[2]_clock_0, , , );
NB1_q_b[2]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[2]_PORT_B_address_reg = DFFE(NB1_q_b[2]_PORT_B_address, NB1_q_b[2]_clock_1, , , );
NB1_q_b[2]_PORT_A_write_enable = GND;
NB1_q_b[2]_PORT_A_write_enable_reg = DFFE(NB1_q_b[2]_PORT_A_write_enable, NB1_q_b[2]_clock_0, , , );
NB1_q_b[2]_PORT_B_write_enable = PB1L92;
NB1_q_b[2]_PORT_B_write_enable_reg = DFFE(NB1_q_b[2]_PORT_B_write_enable, NB1_q_b[2]_clock_1, , , );
NB1_q_b[2]_clock_0 = CLK;
NB1_q_b[2]_clock_1 = A1L5;
NB1_q_b[2]_PORT_B_data_out = MEMORY(NB1_q_b[2]_PORT_A_data_in_reg, NB1_q_b[2]_PORT_B_data_in_reg, NB1_q_b[2]_PORT_A_address_reg, NB1_q_b[2]_PORT_B_address_reg, NB1_q_b[2]_PORT_A_write_enable_reg, NB1_q_b[2]_PORT_B_write_enable_reg, , , NB1_q_b[2]_clock_0, NB1_q_b[2]_clock_1, , , , );
NB1_q_b[2] = NB1_q_b[2]_PORT_B_data_out[0];


--NB1_q_a[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[1]_PORT_A_data_in = VCC;
NB1_q_a[1]_PORT_A_data_in_reg = DFFE(NB1_q_a[1]_PORT_A_data_in, NB1_q_a[1]_clock_0, , , );
NB1_q_a[1]_PORT_B_data_in = PB1_ram_rom_data_reg[1];
NB1_q_a[1]_PORT_B_data_in_reg = DFFE(NB1_q_a[1]_PORT_B_data_in, NB1_q_a[1]_clock_1, , , );
NB1_q_a[1]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_a[1]_PORT_A_address_reg = DFFE(NB1_q_a[1]_PORT_A_address, NB1_q_a[1]_clock_0, , , );
NB1_q_a[1]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_a[1]_PORT_B_address_reg = DFFE(NB1_q_a[1]_PORT_B_address, NB1_q_a[1]_clock_1, , , );
NB1_q_a[1]_PORT_A_write_enable = GND;
NB1_q_a[1]_PORT_A_write_enable_reg = DFFE(NB1_q_a[1]_PORT_A_write_enable, NB1_q_a[1]_clock_0, , , );
NB1_q_a[1]_PORT_B_write_enable = PB1L92;
NB1_q_a[1]_PORT_B_write_enable_reg = DFFE(NB1_q_a[1]_PORT_B_write_enable, NB1_q_a[1]_clock_1, , , );
NB1_q_a[1]_clock_0 = CLK;
NB1_q_a[1]_clock_1 = A1L5;
NB1_q_a[1]_PORT_A_data_out = MEMORY(NB1_q_a[1]_PORT_A_data_in_reg, NB1_q_a[1]_PORT_B_data_in_reg, NB1_q_a[1]_PORT_A_address_reg, NB1_q_a[1]_PORT_B_address_reg, NB1_q_a[1]_PORT_A_write_enable_reg, NB1_q_a[1]_PORT_B_write_enable_reg, , , NB1_q_a[1]_clock_0, NB1_q_a[1]_clock_1, , , , );
NB1_q_a[1] = NB1_q_a[1]_PORT_A_data_out[0];

--NB1_q_b[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[1]
NB1_q_b[1]_PORT_A_data_in = VCC;
NB1_q_b[1]_PORT_A_data_in_reg = DFFE(NB1_q_b[1]_PORT_A_data_in, NB1_q_b[1]_clock_0, , , );
NB1_q_b[1]_PORT_B_data_in = PB1_ram_rom_data_reg[1];
NB1_q_b[1]_PORT_B_data_in_reg = DFFE(NB1_q_b[1]_PORT_B_data_in, NB1_q_b[1]_clock_1, , , );
NB1_q_b[1]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[1]_PORT_A_address_reg = DFFE(NB1_q_b[1]_PORT_A_address, NB1_q_b[1]_clock_0, , , );
NB1_q_b[1]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[1]_PORT_B_address_reg = DFFE(NB1_q_b[1]_PORT_B_address, NB1_q_b[1]_clock_1, , , );
NB1_q_b[1]_PORT_A_write_enable = GND;
NB1_q_b[1]_PORT_A_write_enable_reg = DFFE(NB1_q_b[1]_PORT_A_write_enable, NB1_q_b[1]_clock_0, , , );
NB1_q_b[1]_PORT_B_write_enable = PB1L92;