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		Floating Point IIR using software pipelining

Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062

This program implements a Floating point IIR using software pipelining
It can be compiled and run on ADSP-TS101 and ADSP-TS201.

Files contained in this directory:
iir_flp32_pipe_TS201.tcl	builds the project and saves the output buffer into an output file
iir_flp32_pipe_TS101.tcl	builds the project and saves the output buffer into an output file
ADSP-TS101_ASM.ldf		Linker Description File
ADSP-TS201_ASM.ldf		Linker Description File
iir_flp32_pipe_TS101.dpj	VisualDSP project file
iir_flp32_pipe_TS201.dpj	VisualDSP project file
iir_flp32_pipe.asm		Floating Point IIR using software pipelining
Cache_macros.h			TS201S macro file which includes macros to enable the cache
coeffs.dat
indata.dat
output.dat
IIR_FLP32_PIPE.txt		This readme file

Description:
This program is a 32-bit floating point IIR filter.  
It uses a software pipelined cascade biquad. It has a minimum of 4 biquad.  
The code is highly optimized, but there is a latency due to the pipeline.
See the source file for more information.