; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                     ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; gray_counter.v                   ; yes             ; User Verilog HDL File  ; D:/iii/gray_counter.v        ;
+----------------------------------+-----------------+------------------------+------------------------------+


+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary              ;
+---------------------------------------------+------------+
; Resource                                    ; Usage      ;
+---------------------------------------------+------------+
; Estimated Total logic elements              ; 8          ;
;                                             ;            ;
; Total combinational functions               ; 8          ;
; Logic element usage by number of LUT inputs ;            ;
;     -- 4 input functions                    ; 1          ;
;     -- 3 input functions                    ; 1          ;
;     -- <=2 input functions                  ; 6          ;
;                                             ;            ;
; Logic elements by mode                      ;            ;
;     -- normal mode                          ; 8          ;
;     -- arithmetic mode                      ; 0          ;
;                                             ;            ;
; Total registers                             ; 3          ;
;     -- Dedicated logic registers            ; 3          ;
;     -- I/O registers                        ; 0          ;
;                                             ;            ;
; I/O pins                                    ; 0          ;
; Maximum fan-out node                        ; counter[2] ;
; Maximum fan-out                             ; 4          ;
; Total fan-out                               ; 28         ;
; Average fan-out                             ; 1.47       ;
+---------------------------------------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |gray_counter              ; 8 (8)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |gray_counter       ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |gray_counter ;
+----------------+-------+-----------------------------------------------------+
; Parameter Name ; Value ; Type                                                ;
+----------------+-------+-----------------------------------------------------+
; bits           ; 3     ; Signed Integer                                      ;
+----------------+-------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Oct 22 19:04:41 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gray_counter -c gray_counter
Info: Found 1 design units, including 1 entities, in source file gray_counter.v
    Info: Found entity 1: gray_counter
Info: Elaborating entity "gray_counter" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at gray_counter.v(11): truncated value with size 32 to match size of target (3)
Info: Implemented 16 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 6 output pins
    Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 127 megabytes of memory during processing
    Info: Processing ended: Mon Oct 22 19:04:43 2007
    Info: Elapsed time: 00:00:02