/******************************************************************************/
/* Ext_RAM.INI: External RAM (SDRAM) Initialization File for NXP LPC2468      */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>                           // 
/******************************************************************************/
/* This file is part of the uVision/ARM development tools.                    */
/* Copyright (c) 2005-2007 Keil Software. All rights reserved.                */
/* This software may only be used under the terms of a valid, current,        */
/* end user licence from KEIL for a compatible version of KEIL software       */
/* development tools. Nothing else gives you the right to use this software.  */
/******************************************************************************/


FUNC void SetupForStart (void) {

// <o> Program Entry Point
  PC = 0xA0000000;
}


FUNC void Init (void) {

  if (_RDWORD(0xE01FC088) & (1 << 25)) {
    _WDWORD(0xE01FC080, 0x00000001);    // PLLCON
    _WDWORD(0xE01FC08C, 0x000000AA);    // PLLFEED
    _WDWORD(0xE01FC08C, 0x00000055);    // PLLFEED
  }

  // Disable PLL
  _WDWORD(0xE01FC080, 0x00000000);      // PLLCON
  _WDWORD(0xE01FC08C, 0x000000AA);      // PLLFEED
  _WDWORD(0xE01FC08C, 0x00000055);      // PLLFEED

  // Setup Clock: XTAL = 12 MHz => PLL = 288 MHz, Processor Clock = 57.6 MHz
  _WDWORD(0xE01FC1A0, 0x00000020);      // SCS: Enable main oscillator
  _sleep_ (100);                        // Wait for main oscillator to stabilize
  _WDWORD(0xE01FC10C, 0x00000001);      // CLKSRCSEL: Select PLL source clock
  _WDWORD(0xE01FC084, 0x0000000B);      // PLLCFG
  _WDWORD(0xE01FC08C, 0x000000AA);      // PLLFEED
  _WDWORD(0xE01FC08C, 0x00000055);      // PLLFEED
  _WDWORD(0xE01FC080, 0x00000001);      // PLLCON
  _WDWORD(0xE01FC08C, 0x000000AA);      // PLLFEED
  _WDWORD(0xE01FC08C, 0x00000055);      // PLLFEED
  _sleep_ (100);                        // Wait for PLL lock
  _WDWORD(0xE01FC104, 0x00000004);      // CCLKCFG: Setup CPU clock divider
  _WDWORD(0xE01FC108, 0x00000005);      // USBCLKCFG: Setup USB clock divider
  _WDWORD(0xE01FC1A8, 0x00000000);      // PCLKSEL0: Setup peripheral clock dividers
  _WDWORD(0xE01FC1AC, 0x00000000);      // PCLKSEL1: Setup peripheral clock dividers
  _WDWORD(0xE01FC080, 0x00000003);      // PLLCON: Switch to PLL clock
  _WDWORD(0xE01FC08C, 0x000000AA);      // PLLFEED
  _WDWORD(0xE01FC08C, 0x00000055);      // PLLFEED
  _sleep_ (100);                        // Wait for PLL lock

  // SDRAM Setup
  _WDWORD(0xFFE08000, 0x00000001);      // EMC_CTRL: Disable address mirror
  _WDWORD(0xE01FC0C4, 0x00000800);      // PCONP: Turn on EMC PCLK
  _WDWORD(0xE002C014, 0x05010115);      // PINSEL5
  _WDWORD(0xE002C018, 0x55555555);      // PINSEL6
  _WDWORD(0xE002C020, 0x55555555);      // PINSEL8
  _WDWORD(0xE002C024, 0x50055555);      // PINSEL9

  _WDWORD(0xFFE08030, 0x00000002);      // EMC_DYN_RP:   Command period: 3 clock cycles
  _WDWORD(0xFFE08034, 0x00000003);      // EMC_DYN_RAS:  RAS command period: 4 clock cycles     
  _WDWORD(0xFFE08038, 0x00000007);      // EMC_DYN_SREX: Self-refresh period: 8 clock cycles    
  _WDWORD(0xFFE0803C, 0x00000002);      // EMC_DYN_APR:  Data out to active: 3 clock cycles     
  _WDWORD(0xFFE08040, 0x00000005);      // EMC_DYN_DAL:  Data in to active: 5 clock cycles      
  _WDWORD(0xFFE08044, 0x00000001);      // EMC_DYN_WR:   Write recovery: 2 clock cycles         
  _WDWORD(0xFFE08048, 0x00000005);      // EMC_DYN_RC:   Active to Active cmd: 6 clock cycles   
  _WDWORD(0xFFE0804C, 0x00000005);      // EMC_DYN_RFC:  Auto-refresh: 6 clock cycles           
  _WDWORD(0xFFE08050, 0x00000007);      // EMC_DYN_XSR:  Exit self-refresh: 8 clock cycles      
  _WDWORD(0xFFE08054, 0x00000001);      // EMC_DYN_RRD:  Active bank A->B: 2 clock cycles       
  _WDWORD(0xFFE08058, 0x00000002);      // EMC_DYN_MRD:  Load Mode to Active cmd: 3 clock cycles

  _WDWORD(0xFFE08028, 0x00000001);      // EMC_DYN_RD_CFG: Command delayed strategy      

  _WDWORD(0xFFE08104, 0x00000303);      // EMC_DYN_RASCAS0: Default setting, RAS latency 3 CCLKs, CAS latenty 3 CCLKs      

  _WDWORD(0xFFE08100, 0x00000680);      // EMC_DYN_CFG0: 256MB, 16Mx16, 4 banks, row=13, column=9      
  _sleep_ (100);                        // Wait 100 ms  

  _WDWORD(0xFFE08020, 0x00000183);      // EMC_DYN_CTRL: Mem clock enable, CLKOUT runs, send command: NOP      
  _sleep_ (200);                        // Wait 200 ms  
    
  _WDWORD(0xFFE08020, 0x00000103);      // EMC_DYN_CTRL: Send command: PRECHARGE-ALL, shortest possible refresh period      

  _WDWORD(0xFFE08024, 0x00000002);      // EMC_DYN_RFSH: Set 32 CCLKs between SDRAM refresh cycles      
  _sleep_ (1);                          // Wait 1   ms  
    
  _WDWORD(0xFFE08024, 0x0000001C);      // EMC_DYN_RFSH: Set 28 x 16CCLKs=448CCLK=7.5us between SDRAM refresh cycles      
    
  _WDWORD(0xFFE08020, 0x00000083);      // EMC_DYN_CTRL: Mem clock enable, CLKOUT runs, send command: MODE      

  _RDWORD(0xA0033000);                  // Dummy read
  
  _WDWORD(0xFFE08020, 0x00000000);      // EMC_DYN_CTRL: Send command: NORMAL      

  _WDWORD(0xFFE08100, 0x00080680);      // EMC_DYN_CFG0: Enable buffer      
  _sleep_ (1);                          // Wait 1   ms  
}


Init();                                 // Initialize memory
LOAD Ext_SDRAM\Blinky.axf INCREMENTAL   // Download program
SetupForStart();                        // Setup for Running
g, main                                 // Goto Main