/*****************************************************************************
Copyright(c) 2005 Analog Devices, Inc.  All Rights Reserved. This software is
proprietary and confidential to Analog Devices, Inc. and its licensors.
******************************************************************************

$RCSfile: jpeg_mjpeg_cache.h,v $
$Revision: 1.1 $
$Date: 2006/07/21 08:02:56 $

Project:	BlackfinSDK (JPEG Edge Detection)
Title:		cache services
Author(s):	ku
Revised by: dwu, bmk

Description:
			Controls instruction/data caches

References:
			None

******************************************************************************
Tab Setting:			4

Target Processor:		ADSP-BF5xx
Target Tools Revision:	ADSP VisualDSP++ v4.5
******************************************************************************

Modification History:
====================
$Log: jpeg_mjpeg_cache.h,v $
Revision 1.1  2006/07/21 08:02:56  bmk
JPEG common files


*****************************************************************************/

#ifndef __JPEG_MJPEG_CACHE_H__
#define __JPEG_MJPEG_CACHE_H__

#include <services/services.h>			// system services include

// data cache utilities
// L1 Data Memory Control Register
inline void disable_data_cache(void)
{
	*pDMEM_CONTROL &= ~0xA;		//disable CPLB's, DMC in reserved mode
	ssync();
}

inline void enable_data_cache(void)
{
	*pDMEM_CONTROL |= 0xA;		//enable CPLB's, Data Bank A is lower 16K byte SRAM, upper 16K byte cache, Data Bank B is SRAM
	ssync();
}

// instruction cache utilities
// L1 Instruction Memory Control Register
inline void disable_instruction_cache(void)
{
	*pIMEM_CONTROL &= ~0x4;		// disable CPLB's, All cacheways locked
	ssync();
}

inline void enable_instruction_cache(void)
{
	*pIMEM_CONTROL |= 0x4;		// enable CPLB's, Upper 16K byte of L1 instruction memory configured as cache
	ssync();
}

// Function declarations
void configure_data_cache_cplbs(int dcplb_table[16][2]);
void configure_instruction_cache_cplbs(int icplb_table[16][2]);

#endif 	// __JPEG_MJPEG_CACHE_H__