/* MANAGED-BY-SYSTEM-BUILDER                                    *//*** ADSP-BF537 linker description file generated on Dec 21, 2006 at 10:15:33.**** Copyright (C) 2000-2006 Analog Devices Inc., All Rights Reserved.**** This file is generated automatically based upon the options selected** in the LDF Wizard. Changes to the LDF configuration should be made by ** changing the appropriate options rather than editing this file. **** Configuration:-**     crt_doj:                                .\Debug\bf_test_basiccrt.doj**     processor:                              ADSP-BF537**     si_revision:                            automatic**     cplb_init_cplb_ctrl:                    (**                                              CPLB_ENABLE_ICACHE**                                              CPLB_ENABLE_DCACHE**                                              CPLB_ENABLE_CPLBS**                                              CPLB_ENABLE_ICPLBS**                                              CPLB_ENABLE_DCPLBS**                                             )**     using_cplusplus:                        true**     mem_init:                               false**     use_vdk:                                false**     use_eh:                                 true**     use_argv:                               false**     running_from_internal_memory:           true**     user_heap_src_file:                     F:\bf_sdk\test_bed\537\bf_test_heaptab.c**     libraries_use_stdlib:                   true**     libraries_use_fileio_libs:              false**     libraries_use_ieeefp_emulation_libs:    false**     libraries_use_eh_enabled_libs:          false**     system_heap:                            L1**     system_heap_min_size:                   2K**     system_stack:                           L1**     system_stack_min_size:                  2K**     use_sdram:                              true**     use_sdram_size:                         64M**     use_sdram_partitioned:                  default***/ARCHITECTURE(ADSP-BF537)SEARCH_DIR($ADI_DSP/Blackfin/lib)// Workarounds are enabled, exceptions are disabled.#define RT_LIB_NAME(x) lib ## x ## y.dlb#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb#define RT_OBJ_NAME(x) x ## y.doj#define RT_OBJ_NAME_MT(x) x ## mty.doj      $LIBRARIES = /*$VDSG<insert-user-libraries-at-beginning>                     *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-user-libraries-at-beginning>                     */   RT_LIB_NAME_MT(small532)   ,RT_LIB_NAME_MT(io532)   ,RT_LIB_NAME_MT(c532)   ,RT_LIB_NAME_MT(event532)   ,RT_LIB_NAME_MT(x532)   ,RT_LIB_NAME_EH_MT(cpp532)   ,RT_LIB_NAME_EH_MT(cpprt532)   ,RT_LIB_NAME(f64ieee532)   ,RT_LIB_NAME(dsp532)   ,RT_LIB_NAME(sftflt532)   ,RT_LIB_NAME(etsi532)   ,RT_LIB_NAME(ssl537)   ,RT_LIB_NAME(drv537)   ,RT_OBJ_NAME_MT(idle532)   ,RT_LIB_NAME_MT(rt_fileio532)/*$VDSG<insert-user-libraries-at-end>                           *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-user-libraries-at-end>                           */   ;$OBJS_LIBS_INTERNAL = /*$VDSG<insert-libraries-internal>                              *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-libraries-internal>                              */   $OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")}/*$VDSG<insert-libraries-internal-end>                          *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-libraries-internal-end>                          */   ;$OBJS_LIBS_NOT_EXTERNAL = /*$VDSG<insert-libraries-not-external>                          *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-libraries-not-external>                          */   $OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")}/*$VDSG<insert-libraries-not-external-end>                      *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-libraries-not-external-end>                      */   ;$OBJECTS =    ".\Debug\bf_test_basiccrt.doj"/*$VDSG<insert-user-objects-at-beginning>                       *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-user-objects-at-beginning>                       */   , RT_LIB_NAME(profile532)   , $COMMAND_LINE_OBJECTS   , "cplbtab533.doj"/*$VDSG<insert-user-objects-at-end>                             *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-user-objects-at-end>                             */   , RT_OBJ_NAME(crtn532)   ;/*$VDSG<insert-user-macros>                                     *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-user-macros>                                     *//*$VDSG<customise-async-macros>                                 *//* This code is preserved if the LDF is re-generated.           */#define ASYNC0_MEMTYPE RAM#define ASYNC1_MEMTYPE RAM#define ASYNC2_MEMTYPE RAM#define ASYNC3_MEMTYPE RAM/*$VDSG<customise-async-macros>                                 */MEMORY{/*** ADSP-BF537 MEMORY MAP.**** The known memory spaces are as follows:**** 0xFFE00000 - 0xFFFFFFFF  Core MMR registers (2MB)** 0xFFC00000 - 0xFFDFFFFF  System MMR registers (2MB)** 0xFFB01000 - 0xFFBFFFFF  Reserved** 0xFFB00000 - 0xFFB00FFF  Scratch SRAM (4K)** 0xFFA14000 - 0xFFAFFFFF  Reserved** 0xFFA10000 - 0XFFA13FFF  Code SRAM/CACHE (16K)** 0xFFA0C000 - 0xFFA0FFFF  Reserved** 0xFFA08000 - 0xFFA0BFFF  Instruction Bank B SRAM (16K)** 0xFFA00000 - 0xFFA07FFF  Instruction Bank A SRAM (32K)** 0xFF908000 - 0xFF9FFFFF  Reserved** 0xFF904000 - 0xFF907FFF  Data Bank B SRAM/CACHE (16K)** 0xFF900000 - 0XFF903FFF  Data Bank B SRAM (16K)** 0xFF808000 - 0xFF8FFFFF  Reserved** 0xFF804000 - 0xFF807FFF  Data Bank A SRAM/CACHE (16K)** 0xFF800000 - 0XFF803FFF  Data Bank A SRAM (16K)** 0xEF000800 - 0xFF800000  Reserved** 0xEF000000 - 0xFF8007FF  Boot ROM (2K)** 0x20400000 - 0xEEFFFFFF  Reserved** 0x20300000 - 0x203FFFFF  ASYNC MEMORY BANK 3 (1MB)** 0x20200000 - 0x202FFFFF  ASYNC MEMORY BANK 2 (1MB)** 0x20100000 - 0x201FFFFF  ASYNC MEMORY BANK 1 (1MB)** 0x20000000 - 0x200FFFFF  ASYNC MEMORY BANK 0 (1MB)** 0x00000000 - 0x1FFFFFFF  SDRAM MEMORY (16MB - 512MB)** ** Notes:** 0xFF807FEF-0xFF807FFF**   Required by boot-loader. Used as heap or cache below which is ok. Cannot**   contain initialized data or code.*/   MEM_SYS_MMRS            { TYPE(RAM) START(0xFFC00000) END(0xFFDFFFFF) WIDTH(8) }   MEM_L1_SCRATCH          { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }   MEM_L1_CODE_CACHE       { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }   MEM_L1_CODE             { TYPE(RAM) START(0xFFA00000) END(0xFFA0BFFF) WIDTH(8) }   MEM_L1_DATA_B           { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }   MEM_L1_DATA_A_CACHE     { TYPE(RAM) START(0xFF804000) END(0xFF807FFF) WIDTH(8) }   MEM_L1_DATA_A           { TYPE(RAM) START(0xFF800000) END(0xFF803FFF) WIDTH(8) }   MEM_ASYNC3              { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) }   MEM_ASYNC2              { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) }   MEM_ASYNC1              { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) }   MEM_ASYNC0              { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) }   MEM_SDRAM0_BANK0        { TYPE(RAM) START(0x00000004) END(0x00ffffff) WIDTH(8) }    MEM_SDRAM0_BANK1        { TYPE(RAM) START(0x01000000) END(0x01ffffff) WIDTH(8) }    MEM_SDRAM0_BANK2        { TYPE(RAM) START(0x02000000) END(0x02ffffff) WIDTH(8) }    MEM_SDRAM0_BANK3        { TYPE(RAM) START(0x03000000) END(0x03ffffff) WIDTH(8) }       /*$VDSG<insert-new-memory-segments>                          */   /* Text inserted between these $VDSG comments will be preserved */   /*$VDSG<insert-new-memory-segments>                          */   } /* MEMORY */PROCESSOR p0{   OUTPUT($COMMAND_LINE_OUTPUT_FILE)   RESOLVE(start, 0xFFA00000)   KEEP(start, _main)      /*$VDSG<insert-user-ldf-commands>                            */   /* Text inserted between these $VDSG comments will be preserved */   /*$VDSG<insert-user-ldf-commands>                            */      SECTIONS   {      /* Workaround for hardware errata 05-00-0189 -       ** "Speculative (and fetches made at boundary of reserved memory      ** space) for instruction or data fetches may cause false      ** protection exceptions".      **       ** Done by avoiding use of 76 bytes from at the end of blocks      ** that are adjacent to reserved memory. Workaround is enabled       ** for appropriate silicon revisions (-si-revision switch).      */      RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76)      RESERVE(___wab1=MEMORY_END(MEM_L1_CODE) - 75, ___l1 = 76)      RESERVE(___wab4=MEMORY_END(MEM_L1_DATA_B) - 75, ___l4 = 76)      RESERVE(___wab5=MEMORY_END(MEM_L1_DATA_A_CACHE) - 75, ___l5 = 76)      RESERVE(___wab7=MEMORY_END(MEM_ASYNC3) - 75, ___l7 = 76)      RESERVE(___wab8=MEMORY_END(MEM_SDRAM0_BANK3) - 75, ___l8 = 76)            /*$VDSG<insert-new-sections-at-the-start>                 */      /* Text inserted between these $VDSG comments will be preserved */      /*$VDSG<insert-new-sections-at-the-start>                 */            scratchpad      {         INPUT_SECTION_ALIGN(4)                  /*$VDSG<insert-input-sections-at-the-start-of-scratchpad>  */         /* Text inserted between these $VDSG comments will be preserved */         /*$VDSG<insert-input-sections-at-the-start-of-scratchpad>  */