?? initialize.c
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#include <services\services.h> // system services
#include <sysreg.h>
#include "initialize.h"
#include "adv7180.h"
#include "WatchDog.h"
static void Init_Timers(void)
{
#if defined(__ADSP_EDINBURGH__)
*pTIMER_DISABLE = TIMDIS0;
*pTIMER0_CONFIG = PWM_OUT | PERIOD_CNT | IRQ_ENA;
*pTIMER0_PERIOD = SECONDS * SYSCLK;
*pTIMER0_WIDTH = SECONDS * SYSCLK / 2;
*pTIMER_ENABLE = TIMEN0;
#endif
ssync();
}
static void init_SDRAM(void)
{
#if defined(__ADSP_EDINBURGH__)
*pEBIU_AMBCTL0 = 0xffc2ffc2;
*pEBIU_AMBCTL1 = 0xffc2ffc2;
//*pEBIU_AMGCTL = 0x000F; // |Enable all memory banks
*pEBIU_AMGCTL = 0x00F8;
ssync();
if (*pEBIU_SDSTAT & SDRS) {
//SDRAM Refresh Rate Control Register
*pEBIU_SDRRC = 0x0817;
//SDRAM Memory Bank Control Register
*pEBIU_SDBCTL = 0x0013;
//SDRAM Memory Global Control Register
*pEBIU_SDGCTL = 0x0091998d;
ssync();
}
#endif
#if defined(__ADSP_BRAEMAR__)
// Initalize EBIU control registers to enable all banks
*pEBIU_AMBCTL0 = 0xffc2ffc2;
*pEBIU_AMBCTL1 = 0xffc2ffc2;
*pEBIU_AMGCTL = 0x00F8;
ssync();
// Check if already enabled
if( SDRS != ((*pEBIU_SDSTAT) & SDRS) )
{
return;
}
//SDRAM Refresh Rate Control Register
*pEBIU_SDRRC = 0x0817; //0x03A3;
//SDRAM Memory Bank Control Register
*pEBIU_SDBCTL = 0x0013;
//SDRAM Memory Global Control Register
*pEBIU_SDGCTL = 0x0091998d;//0x998D0491;
ssync();
#endif
#if defined(__ADSP_TETON__)
*pEBIU_AMGCTL = 0x00F8;
// 要將bank0的ARDY置0
*pEBIU_AMBCTL0 = 0xffc2ffc2;
*pEBIU_AMBCTL1 = 0xffc2ffc2;
ssync();
if (*pEBIU_SDSTAT & SDRS) {
*pEBIU_SDBCTL = 0x00000015; //SDRAM Memory Bank Control Register
ssync();
*pEBIU_SDRRC = 0x000003a9; //SDRAM Refresh Rate Control Register
ssync();
*pEBIU_SDGCTL = 0x0091998f; //SDRAM Memory Global Control Register
ssync();
}
#endif
}
static void init_PLL(short CoreCLOCK_multiplier, short SCLK_divider)
{
#if defined(__ADSP_EDINBURGH__)
volatile int test=0;
sysreg_write(reg_SYSCFG, 0x32); //Initialize System Configuration Register
*pSIC_IWR = 0x1;
*pPLL_CTL = 0x2000;
*pPLL_DIV = 0x0003; // CSEL= %1, SSEL= %4
ssync();
idle();
#endif
#if defined(__ADSP_BRAEMAR__)
volatile int test=0;
// Initialize System Configuration Register
// enable cycle counter, disable supervisor single step
sysreg_write(reg_SYSCFG, 0x32);
*pSIC_IWR |= 0x1; // enable PLL wakeup
// 537 EZ-Kit Settings fast CCLK, fast SCLK: CCLK = 526.5 MHz, SCLK = 131.625 MHz
*pPLL_CTL = 0x2000; // MSEL= x39, DF= %2
//*pPLL_CTL = 0x3000; // MSEL= x39, DF= %2
*pPLL_DIV = 0x0005; // CSEL= %1, SSEL= %4
*pVR_CTL = 0x40db;
ssync();
idle();
#endif
#if defined(__ADSP_TETON__)
short previous_PLL= *pPLL_CTL;
short previous_SICA_IWR = *pSICA_IWR0;
short previous_SICB_IWR = *pSICB_IWR0;
short new_PLL= (previous_PLL & 0x81ff) | ((CoreCLOCK_multiplier & 0x3f) <<9);
if (new_PLL != previous_PLL) { // skip if multiplier has not changed
if ((int)(*pSRAM_BASE_ADDRESS) == 0xFF800000 ) { // do things for Core A
*pSICA_IWR0 = (previous_SICA_IWR | 0x1); // enable PLL Wakeup Interrupt
*pPLL_CTL = new_PLL;
ssync();
idle(); // put in idle
*pSICA_IWR0 = previous_SICA_IWR; // continue here after idle, restore previous IWR content
ssync();
}
else{ // do things for Core B
*pSICB_IWR0 = (previous_SICB_IWR | 0x1); // enable PLL Wakeup Interrupt
ssync();
idle(); // put in idle
*pSICB_IWR0 = previous_SICB_IWR; // continue here after idle, restore previous IWR content
ssync();
} // if (&_CORE == 0)
} // if (new_PLL != previous_PLL)
*pPLL_DIV = (*pPLL_DIV & 0xFFF8) | SCLK_divider;
ssync();
#endif
}//end Init_PLL
static void init_FLAGS(void)
{
#if defined(__ADSP_EDINBURGH__)
int i = 0; short temp = 0;
// Initialize ports
*pFIO_DIR = *pFIO_DIR | 0x0040; //PF6,PF7輸出0
*pFIO_FLAG_C = 0x0040;
asm("ssync;");
//*pFIO_DIR = *pFIO_DIR | 0x0180; //PF7,PF8輸出0
//*pFIO_FLAG_C = 0x0180;
//asm("ssync;");
#endif
#if defined(__ADSP_BRAEMAR__)
int i = 0; short temp = 0;
// Initialize ports
temp = *pPORTG_FER;
asm("ssync;");
temp = 0x00FF;
*pPORTG_FER = temp;
asm("ssync;");
*pPORTG_FER = temp;
asm("ssync;");
temp = *pPORTF_FER;
asm("ssync;");
temp = 0xFBA0;
*pPORTF_FER = temp;
asm("ssync;");
*pPORTF_FER = temp;
asm("ssync;");
temp = *pPORT_MUX;
asm("ssync;");
temp = 0x0140;
*pPORT_MUX = temp;
asm("ssync;");
*pPORT_MUX = temp;
asm("ssync;");
*pPORTFIO_DIR = *pPORTFIO_DIR | 0x0040; //PF6輸出0
*pPORTFIO_CLEAR = 0x0040;
asm("ssync;");
*pPORTGIO_DIR = *pPORTGIO_DIR | 0x0300; //PF6輸出0
*pPORTGIO_CLEAR = 0x0300;
asm("ssync;");
#endif
#if defined(__ADSP_TETON__)
*pFIO0_DIR = 0x0080; //Activate LEDs On EZ-KIT For Access
*pFIO0_FLAG_C = 0x0080;
#endif
}
static void init_video_codec(void)
{
init_adv7180();
return;
}
static void init_interrupt(void)
{
/*
#if defined(__ADSP_EDINBURGH__)
// configure interrupt
*pSIC_IAR0 = *pSIC_IAR0 & 0xffffffff | 0x00000000;
*pSIC_IAR1 = *pSIC_IAR1 & 0xffffffff | 0x00000001; // map DMA0 PPI Interrupt -> IVG8
*pSIC_IAR2 = *pSIC_IAR2 & 0xffffffff | 0x00600004;
register_handler(ik_ivg8, PPI0_RxIsr); // assign DMA0 PPI ISR to interrupt vector 8
register_handler(ik_ivg13, mDMA_Isr); // assign mDMA_Isr to interrupt vector 13
register_handler(ik_ivg11,Timer0_Isr);
*pILAT |= EVT_IVG8;
*pILAT |= EVT_IVG13;
*pILAT |= EVT_IVG11;
ssync();
*pSIC_IMASK=0x00210100; // all interrupts 0=disabled but DMA0 PPI interrupt enabled
#endif
#if defined(__ADSP_BRAEMAR__)
// configure interrupt
*pSIC_IAR0 = *pSIC_IAR0 & 0xffffffff | 0x00010000;
*pSIC_IAR1 = *pSIC_IAR1 & 0xffffffff | 0x00000000; // map DMA0 PPI Interrupt -> IVG8
*pSIC_IAR2 = *pSIC_IAR2 & 0xffffffff | 0x00000000;
*pSIC_IAR3 = *pSIC_IAR3 & 0xffffffff | 0x00600000;
register_handler(ik_ivg8, PPI0_RxIsr); // assign DMA0 PPI ISR to interrupt vector 8
register_handler(ik_ivg13, mDMA_Isr); // assign mDMA_Isr to interrupt vector 13
*pSIC_IMASK=0x20000010; // all interrupts 0=disabled but DMA0 PPI interrupt enabled
#endif
#if defined(__ADSP_TETON__)
register_handler(ik_ivg8, PPI0_RxIsr); // assign ISR to interrupt vector
register_handler(ik_ivg12,mDMA_Isr);
*pSICA_IAR1 = Peripheral_IVG(11,8); // assign interrupt channel 11 (DMA1_0) to IVG8
*pSICA_IAR6 = Peripheral_IVG(53,12);
*pILAT |= EVT_IVG8; // clear pending IVG8 interrupts
*pILAT |= EVT_IVG12;
ssync();
*pSICA_IMASK0 |= SIC_MASK(11);
*pSICA_IMASK1 |= SIC_MASK(21); //53-32
ssync();
#endif
//TODO: ADD IVG hook
*/
}
void init_hardware(void)
{
init_PLL((short)(CORECLK/CLKIN), (short)(CORECLK/SYSCLK));
init_SDRAM();
init_FLAGS();
init_video_codec();
// init_interrupt();
Init_Timers();
return;
}
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