#include "cplb_tables.h"
#include <cplb.h>

#if defined(__ADSPBF532__) 
int dcplbs_table[16][2] =	{
	// L1 DATA
	{ 0xFF800000,	(PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },	// L1 Data A
	{ 0xFF900000,	(PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },	// L1 Data B
	
	// SDRAM bank 0
	{ 0x00000000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	
	{ 0x00400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE) },	// Slow Heap 1(index 1) Cached , video in frame 0

	// SDRAM bank 1
	{ 0x00800000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	
	{ 0x00C00000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE) },	// Slow Heap 2(index 2) Cached , video in frame 1
	
	// SDRAM bank 2
	{ 0x01000000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// 
	{ 0x01400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE) },	// Slow Heap 3(index 3) Cached , mem dma buffer

	// SDRAM bank 3
	{ 0x01800000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// 
	{ 0x01C00000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// 

	// ASYNC MEMORY
	{ 0x20000000,	(PAGE_SIZE_1MB | CPLB_DDOCACHE) },	// Async Memory Bank 0 (Prim A)
	{ 0x20100000,	(PAGE_SIZE_1MB | CPLB_DDOCACHE) },	// Async Memory Bank 1 (Prim B)
	{ 0x20200000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE) },	// Async Memory Bank 2 (Secnd)
	{ 0x20300000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE) },	// Async Memory Bank 3

	// other SDRAM .... not populated on EZ-kit ... dummy entries
	{ 0x02000000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE) },	// 
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE) }	//
};


int icplbs_table[16][2] =	{
	// L1 CODE
	{ 0xFFA00000,	(PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT)	 },	// L1 Code
	
	// SDRAM bank 0
	{ 0x00000000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// dummy non cached instruction memory (keep free for data heap)
	{ 0x00400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// dummy non cached instruction memory (keep free for data heap)

	// SDRAM bank 1
	{ 0x00800000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory (YUV buffer decoder)
	{ 0x00C00000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// NON Cached Instruction Memory (YUV buffer encoder)
	
	// SDRAM bank 2
	{ 0x01000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory (Video Frame 0)
	{ 0x01400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory

	// SDRAM bank 3
	{ 0x01800000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory (Video Frame 1)
	{ 0x01C00000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory

	// ASYNC MEMORY
	{ 0x20000000,	(PAGE_SIZE_1MB | CPLB_IDOCACHE) },	// Async Memory Bank 0 (Prim A)
	{ 0x20100000,	(PAGE_SIZE_1MB | CPLB_IDOCACHE) },	// Async Memory Bank 1 (Prim B)
	{ 0x20200000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 2 (Second)
	{ 0x20300000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 3

	// other SDRAM .... not populated on EZ-kit ... dummy entries
	{ 0x02000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// 
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// 
	{ 0x02800000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) }	//
};

#endif