// ; $0021_6000 to $0021_6FFF              ;// ;---------------------------------------;// ; Sequencer#define BTA_BASE_ADDR           0x00216000#define BTA_COMMAND             BTA_BASE_ADDR#define BTA_STATUS              BTA_BASE_ADDR#define BTA_PACKETHEAD          (BTA_BASE_ADDR+0x04)#define BTA_PAYLOADHEAD         (BTA_BASE_ADDR+0x08)//// ; BT clocks#define BTA_NATIVECNT           (BTA_BASE_ADDR+0x0C)#define BTA_ESTCNT              (BTA_BASE_ADDR+0x10)#define BTA_OFFSETCNT           (BTA_BASE_ADDR+0x14)#define BTA_NATIVECLK_L         (BTA_BASE_ADDR+0x18)#define BTA_NATIVECLK_H         (BTA_BASE_ADDR+0x1C)#define BTA_ESTCLK_L            (BTA_BASE_ADDR+0x20)#define BTA_ESTCLK_H            (BTA_BASE_ADDR+0x24)#define BTA_OFFSETCLK_L         (BTA_BASE_ADDR+0x28)#define BTA_OFFSETCLK_H         (BTA_BASE_ADDR+0x2C)//// ; BT pipeline#define BTA_HECCRC              (BTA_BASE_ADDR+0x30)#define BTA_WHITE               (BTA_BASE_ADDR+0x34)#define BTA_ENCRYPT             (BTA_BASE_ADDR+0x38)//// ; Radio Control#define BTA_CORR_TIME           (BTA_BASE_ADDR+0x40)#define BTA_RF_GPO              (BTA_BASE_ADDR+0x48)#define BTA_RSSI                (BTA_BASE_ADDR+0x4C)#define BTA_TIME_AB             (BTA_BASE_ADDR+0x50)#define BTA_TIME_CD             (BTA_BASE_ADDR+0x54)#define BTA_PWM_TX              (BTA_BASE_ADDR+0x58)#define BTA_RF_CTRL             (BTA_BASE_ADDR+0x5C)#define BTA_RF_STATUS           (BTA_BASE_ADDR+0x5C)#define BTA_RX_TIME             (BTA_BASE_ADDR+0x60)#define BTA_TX_TIME             (BTA_BASE_ADDR+0x64)// ; Bit Reverse #define BTA_WORD_REV            (BTA_BASE_ADDR+0x178)#define BTA_BYTE_REV            (BTA_BASE_ADDR+0x17C)//// ; Timer#define BTA_TIMER               (BTA_BASE_ADDR+0x68)//// ; Correlator#define BTA_THRESHOLD           (BTA_BASE_ADDR+0x6C)#define BTA_CORR_MAX            (BTA_BASE_ADDR+0x6C)#define BTA_SYNCHWORD_0         (BTA_BASE_ADDR+0x70)#define BTA_SYNCHWORD_1         (BTA_BASE_ADDR+0x74)#define BTA_SYNCHWORD_2         (BTA_BASE_ADDR+0x78)#define BTA_SYNCHWORD_3         (BTA_BASE_ADDR+0x7C)//// ; BitBUF#define BTA_BUF_WORD_0          (BTA_BASE_ADDR+0x80)#define BTA_BUF_WORD_1          (BTA_BASE_ADDR+0x84)#define BTA_BUF_WORD_2          (BTA_BASE_ADDR+0x88)#define BTA_BUF_WORD_3          (BTA_BASE_ADDR+0x8C)#define BTA_BUF_WORD_4          (BTA_BASE_ADDR+0x90)#define BTA_BUF_WORD_5          (BTA_BASE_ADDR+0x94)#define BTA_BUF_WORD_6          (BTA_BASE_ADDR+0x98)#define BTA_BUF_WORD_7          (BTA_BASE_ADDR+0x9C)#define BTA_BUF_WORD_8          (BTA_BASE_ADDR+0xA0)#define BTA_BUF_WORD_9          (BTA_BASE_ADDR+0xA4)#define BTA_BUF_WORD_10         (BTA_BASE_ADDR+0xA8)#define BTA_BUF_WORD_11         (BTA_BASE_ADDR+0xAC)#define BTA_BUF_WORD_12         (BTA_BASE_ADDR+0xB0)#define BTA_BUF_WORD_13         (BTA_BASE_ADDR+0xB4)#define BTA_BUF_WORD_14         (BTA_BASE_ADDR+0xB8)#define BTA_BUF_WORD_15         (BTA_BASE_ADDR+0xBC)#define BTA_BUF_WORD_16         (BTA_BASE_ADDR+0xC0)#define BTA_BUF_WORD_17         (BTA_BASE_ADDR+0xC4)#define BTA_BUF_WORD_18         (BTA_BASE_ADDR+0xC8)#define BTA_BUF_WORD_19         (BTA_BASE_ADDR+0xCC)#define BTA_BUF_WORD_20         (BTA_BASE_ADDR+0xD0)#define BTA_BUF_WORD_21         (BTA_BASE_ADDR+0xD4)#define BTA_BUF_WORD_22         (BTA_BASE_ADDR+0xD8)#define BTA_BUF_WORD_23         (BTA_BASE_ADDR+0xDC)#define BTA_BUF_WORD_24         (BTA_BASE_ADDR+0xE0)#define BTA_BUF_WORD_25         (BTA_BASE_ADDR+0xE4)#define BTA_BUF_WORD_26         (BTA_BASE_ADDR+0xE8)#define BTA_BUF_WORD_27         (BTA_BASE_ADDR+0xEC)#define BTA_BUF_WORD_28         (BTA_BASE_ADDR+0xF0)#define BTA_BUF_WORD_29         (BTA_BASE_ADDR+0xF4)#define BTA_BUF_WORD_30         (BTA_BASE_ADDR+0xF8)#define BTA_BUF_WORD_31         (BTA_BASE_ADDR+0xFC)//                                                 // ; Wakeup                                        #define BTA_WU_1                (BTA_BASE_ADDR+0x100)#define BTA_WU_2                (BTA_BASE_ADDR+0x104)#define BTA_WU_3                (BTA_BASE_ADDR+0x108)#define BTA_WU_DELTA3           (BTA_BASE_ADDR+0x108)#define BTA_WU_4                (BTA_BASE_ADDR+0x10C)#define BTA_WU_DELTA4           (BTA_BASE_ADDR+0x10C)#define BTA_WU_CTRL             (BTA_BASE_ADDR+0x110)#define BTA_WU_STATUS           (BTA_BASE_ADDR+0x110)#define BTA_WU_COUNT            (BTA_BASE_ADDR+0x114)//// ; Clock control#define BTA_CLK_CTRL            (BTA_BASE_ADDR+0x118)//// ; SPI#define BTA_SPI_WORD_0          (BTA_BASE_ADDR+0x120)#define BTA_SPI_WORD_1          (BTA_BASE_ADDR+0x124)#define BTA_SPI_WORD_2          (BTA_BASE_ADDR+0x128)#define BTA_SPI_WORD_3          (BTA_BASE_ADDR+0x12C)#define BTA_SPI_WADDR           (BTA_BASE_ADDR+0x130)#define BTA_SPI_RADDR           (BTA_BASE_ADDR+0x134)#define BTA_SPI_CTRL            (BTA_BASE_ADDR+0x138)#define BTA_SPI_STATUS          (BTA_BASE_ADDR+0x138)//                                                 // ; Frequency Hopping                             #define BTA_HOPWORDS_0          (BTA_BASE_ADDR+0x140)#define BTA_FREQ_OUT            (BTA_BASE_ADDR+0x140)#define BTA_HOPWORDS_1          (BTA_BASE_ADDR+0x144)#define BTA_HOPWORDS_2          (BTA_BASE_ADDR+0x148)#define BTA_HOPWORDS_3          (BTA_BASE_ADDR+0x14C)#define BTA_HOPWORDS_4          (BTA_BASE_ADDR+0x150)//// ; Interrupt#define BTA_INTERRUPT           (BTA_BASE_ADDR+0x160)//// ; MLSE#define BTA_SYNC_METRIC         (BTA_BASE_ADDR+0x170)#define BTA_SYNC_FC             (BTA_BASE_ADDR+0x174)//// ;---------------------------------------;// ; Clock & Reset (CRM)                   ;// ; $0021_B000 to $0021_BFFF              ;// ;---------------------------------------;#define CRM_BASE_ADDR           0x0021B000#define CRM_CSCR                CRM_BASE_ADDR	// ; Clock Source Control Reg#define CRM_MPCTL0              (CRM_BASE_ADDR+0x04)	// ; MCU PLL Control Reg#define CRM_MPCTL1              (CRM_BASE_ADDR+0x08)	// ; MCU PLL & System Clk Ctl Reg#define CRM_UPCTL0              (CRM_BASE_ADDR+0x0C)	// ; USB PLL Control Reg 0#define CRM_UPCTL1              (CRM_BASE_ADDR+0x10)	// ; USB PLL Control Reg 1#define CRM_PCDR                (CRM_BASE_ADDR+0x20)	// ; Perpheral Clock Divider Reg//#define CRM_RSR                 (CRM_BASE_ADDR+0x800)	// ; Reset Source Reg#define CRM_SIDR                (CRM_BASE_ADDR+0x804)	// ; Silicon ID Reg#define CRM_FMCR                (CRM_BASE_ADDR+0x808)	// ; Functional Muxing Control Reg#define CRM_GPCR                (CRM_BASE_ADDR+0x80C)	// ; Global Control Reg// ;---------------------------------------;// ; CSI// ; $0022_4000 to $0022_4FFF              ;// ;---------------------------------------;#define CSI_BASE_ADDR           0xF0224000#define CSI_CTRL_REG1           (CSI_BASE_ADDR+0x00)#define CSI_CTRL_REG2           (CSI_BASE_ADDR+0x04)#define CSI_STS_REG             (CSI_BASE_ADDR+0x08)#define CSI_STAT_FIFO           (CSI_BASE_ADDR+0x0C)#define CSI_RX_FIFO             (CSI_BASE_ADDR+0x10)//// ;---------------------------------------;// ; CSPI                                  ;// ; $0021_3000 to $0021_3FFF              ;// ;---------------------------------------;#define CSPI_BASE_ADDR          0x00213000#define CSPI_SPIRXD             CSPI_BASE_ADDR#define CSPI_SPITXD             (CSPI_BASE_ADDR+0x04)#define CSPI_SPICONT1           (CSPI_BASE_ADDR+0x08)#define CSPI_INTCS              (CSPI_BASE_ADDR+0x0C)#define CSPI_SPITEST            (CSPI_BASE_ADDR+0x10)#define CSPI_SPISPCR            (CSPI_BASE_ADDR+0x14)#define CSPI_SPIDMA             (CSPI_BASE_ADDR+0x18)#define CSPI_SPIRESET           (CSPI_BASE_ADDR+0x1C)//// ;---------------------------------------;// ; DMA                                   ;// ; $0020_9000 to $0020_9FFF              ;// ;---------------------------------------;#define DMA_BASE_ADDR           0xF0209000#define DMA_SYS_BASE            (DMA_BASE_ADDR+0x000)#define DMA_M2D_BASE            (DMA_BASE_ADDR+0x040)#define DMA_CH0_BASE            (DMA_BASE_ADDR+0x080)#define DMA_CH1_BASE            (DMA_BASE_ADDR+0x0C0)#define DMA_CH2_BASE            (DMA_BASE_ADDR+0x100)#define DMA_CH3_BASE            (DMA_BASE_ADDR+0x140)#define DMA_CH4_BASE            (DMA_BASE_ADDR+0x180)#define DMA_CH5_BASE            (DMA_BASE_ADDR+0x1C0)#define DMA_CH6_BASE            (DMA_BASE_ADDR+0x200)#define DMA_CH7_BASE            (DMA_BASE_ADDR+0x240)#define DMA_CH8_BASE            (DMA_BASE_ADDR+0x280)#define DMA_CH9_BASE            (DMA_BASE_ADDR+0x2C0)#define DMA_CH10_BASE           (DMA_BASE_ADDR+0x300)#define DMA_TST_BASE            (DMA_BASE_ADDR+0x340)//#define DMA_DCR                 (DMA_SYS_BASE+0x000)#define DMA_ISR                 (DMA_SYS_BASE+0x004)#define DMA_IMR                 (DMA_SYS_BASE+0x008)#define DMA_BTOSR               (DMA_SYS_BASE+0x00C)#define DMA_RTOSR               (DMA_SYS_BASE+0x010)#define DMA_TESR                (DMA_SYS_BASE+0x014)#define DMA_BOSR                (DMA_SYS_BASE+0x018)#define DMA_BTOCR               (DMA_SYS_BASE+0x01C)//#define DMA_WSRA                (DMA_M2D_BASE+0x000)#define DMA_XSRA                (DMA_M2D_BASE+0x004)#define DMA_YSRA                (DMA_M2D_BASE+0x008)#define DMA_WSRB                (DMA_M2D_BASE+0x00C)#define DMA_XSRB                (DMA_M2D_BASE+0x010)#define DMA_YSRB                (DMA_M2D_BASE+0x014)//#define DMA_SAR0                (DMA_CH0_BASE+0x000)#define DMA_DAR0                (DMA_CH0_BASE+0x004)#define DMA_CNTR0               (DMA_CH0_BASE+0x008)#define DMA_CCR0                (DMA_CH0_BASE+0x00C)#define DMA_RSSR0               (DMA_CH0_BASE+0x010)#define DMA_BLR0                (DMA_CH0_BASE+0x014)#define DMA_RTOR0               (DMA_CH0_BASE+0x018)#define DMA_BUCR0               (DMA_CH0_BASE+0x018)//#define DMA_SAR1                (DMA_CH1_BASE+0x000)#define DMA_DAR1                (DMA_CH1_BASE+0x004)#define DMA_CNTR1               (DMA_CH1_BASE+0x008)#define DMA_CCR1                (DMA_CH1_BASE+0x00C)#define DMA_RSSR1               (DMA_CH1_BASE+0x010)#define DMA_BLR1                (DMA_CH1_BASE+0x014)#define DMA_RTOR1               (DMA_CH1_BASE+0x018)#define DMA_BUCR1               (DMA_CH1_BASE+0x018)//#define DMA_SAR2                (DMA_CH2_BASE+0x000)#define DMA_DAR2                (DMA_CH2_BASE+0x004)#define DMA_CNTR2               (DMA_CH2_BASE+0x008)#define DMA_CCR2                (DMA_CH2_BASE+0x00C)#define DMA_RSSR2               (DMA_CH2_BASE+0x010)#define DMA_BLR2                (DMA_CH2_BASE+0x014)#define DMA_RTOR2               (DMA_CH2_BASE+0x018)#define DMA_BUCR2               (DMA_CH2_BASE+0x018)//#define DMA_SAR3                (DMA_CH3_BASE+0x000)#define DMA_DAR3                (DMA_CH3_BASE+0x004)#define DMA_CNTR3               (DMA_CH3_BASE+0x008)#define DMA_CCR3                (DMA_CH3_BASE+0x00C)#define DMA_RSSR3               (DMA_CH3_BASE+0x010)#define DMA_BLR3                (DMA_CH3_BASE+0x014)#define DMA_RTOR3               (DMA_CH3_BASE+0x018)#define DMA_BUCR3               (DMA_CH3_BASE+0x018)//#define DMA_SAR4                (DMA_CH4_BASE+0x000)#define DMA_DAR4                (DMA_CH4_BASE+0x004)#define DMA_CNTR4               (DMA_CH4_BASE+0x008)#define DMA_CCR4                (DMA_CH4_BASE+0x00C)#define DMA_RSSR4               (DMA_CH4_BASE+0x010)#define DMA_BLR4                (DMA_CH4_BASE+0x014)#define DMA_RTOR4               (DMA_CH4_BASE+0x018)#define DMA_BUCR4               (DMA_CH4_BASE+0x018)//#define DMA_SAR5                (DMA_CH5_BASE+0x000)#define DMA_DAR5                (DMA_CH5_BASE+0x004)#define DMA_CNTR5               (DMA_CH5_BASE+0x008)#define DMA_CCR5                (DMA_CH5_BASE+0x00C)#define DMA_RSSR5               (DMA_CH5_BASE+0x010)#define DMA_BLR5                (DMA_CH5_BASE+0x014)#define DMA_RTOR5               (DMA_CH5_BASE+0x018)#define DMA_BUCR5               (DMA_CH5_BASE+0x018)//#define DMA_SAR6                (DMA_CH6_BASE+0x000)#define DMA_DAR6                (DMA_CH6_BASE+0x004)#define DMA_CNTR6               (DMA_CH6_BASE+0x008)#define DMA_CCR6                (DMA_CH6_BASE+0x00C)#define DMA_RSSR6               (DMA_CH6_BASE+0x010)#define DMA_BLR6                (DMA_CH6_BASE+0x014)#define DMA_RTOR6               (DMA_CH6_BASE+0x018)#define DMA_BUCR6               (DMA_CH6_BASE+0x018)//#define DMA_SAR7                (DMA_CH7_BASE+0x000)#define DMA_DAR7                (DMA_CH7_BASE+0x004)#define DMA_CNTR7               (DMA_CH7_BASE+0x008)#define DMA_CCR7                (DMA_CH7_BASE+0x00C)#define DMA_RSSR7               (DMA_CH7_BASE+0x010)#define DMA_BLR7                (DMA_CH7_BASE+0x014)#define DMA_RTOR7               (DMA_CH7_BASE+0x018)#define DMA_BUCR7               (DMA_CH7_BASE+0x018)//#define DMA_SAR8                (DMA_CH8_BASE+0x000)#define DMA_DAR8                (DMA_CH8_BASE+0x004)#define DMA_CNTR8               (DMA_CH8_BASE+0x008)#define DMA_CCR8                (DMA_CH8_BASE+0x00C)#define DMA_RSSR8               (DMA_CH8_BASE+0x010)#define DMA_BLR8                (DMA_CH8_BASE+0x014)#define DMA_RTOR8               (DMA_CH8_BASE+0x018)#define DMA_BUCR8               (DMA_CH8_BASE+0x018)//#define DMA_SAR9                (DMA_CH9_BASE+0x000)#define DMA_DAR9                (DMA_CH9_BASE+0x004)#define DMA_CNTR9               (DMA_CH9_BASE+0x008)#define DMA_CCR9                (DMA_CH9_BASE+0x00C)#define DMA_RSSR9               (DMA_CH9_BASE+0x010)#define DMA_BLR9                (DMA_CH9_BASE+0x014)#define DMA_RTOR9               (DMA_CH9_BASE+0x018)#define DMA_BUCR9               (DMA_CH9_BASE+0x018)//#define DMA_SAR10               (DMA_CH10_BASE+0x000)#define DMA_DAR10               (DMA_CH10_BASE+0x004)#define DMA_CNTR10              (DMA_CH10_BASE+0x008)#define DMA_CCR10               (DMA_CH10_BASE+0x00C)#define DMA_RSSR10              (DMA_CH10_BASE+0x010)#define DMA_BLR10               (DMA_CH10_BASE+0x014)#define DMA_RTOR10              (DMA_CH10_BASE+0x018)#define DMA_BUCR10              (DMA_CH10_BASE+0x018)//                              #define DMA_TCR                 (DMA_TST_BASE+0x000)#define DMA_TFIFOA              (DMA_TST_BASE+0x004)#define DMA_TDRR                (DMA_TST_BASE+0x008)#define DMA_TDIPR               (DMA_TST_BASE+0x00C)#define DMA_TFIFOB              (DMA_TST_BASE+0x010)//                              // ;---------------------------------------;// ; DSPA                                  ;// ; $0022_2000 to $0022_2FFF              ;// ;---------------------------------------;#define DSPA_BASE_ADDR          0x00222000//                              #define DSPA_MAC_MOD            (DSPA_BASE_ADDR+0x0000)#define DSPA_MAC_CTRL           (DSPA_BASE_ADDR+0x0004)#define DSPA_MAC_MULT           (DSPA_BASE_ADDR+0x0008)