/*************************************

	MX1 CSI / iMagic Driver
	
*************************************/
#include "khead.h"
#include "mx1hw.h"
#include "csi.h"

static U32 CSI_ModuleInitDone = 0;


//
//      Module Init
//
static void CSI_ModuleInit(void)
{
	//GPIO init
	*(U32 *) PTA_GIUS &= ~0x00007FF8;

	CSI_ModuleInitDone = 1;

	return;
}


//
//      CSI init
//
void CSI_init(void)
{
	if (!CSI_ModuleInitDone)
		CSI_ModuleInit();

	*(U32 *) CSI_CTRL_REG1 = 0x1;	//module enable

//yczhao remove
	*(U32 *) CSI_CTRL_REG1 |= 0x2;	//latch on rising edge

	*(U32 *) CSI_CTRL_REG1 |= 0x10;	//gated clock mode
	*(U32 *) CSI_CTRL_REG1 |= 0x80;	//big endian
	*(U32 *) CSI_CTRL_REG1 |= 0x100;	//sync FIFO clear
	*(U32 *) CSI_CTRL_REG1 |= 0x0200;	//MCLK = HCLK / 2

	*(U32 *) CSI_CTRL_REG1 |= 0x1000;         //HHTech add:set clock divider(=8)
//	*(U32 *) CSI_CTRL_REG1 |= 0x4000;         //HHTech add:set clock divider(=8) //yczhao
	*(U32 *) CSI_CTRL_REG1 |= 0x20000;	//SOF rising edge
	//*(U32 *) CSI_CTRL_REG1 |= 0x10000;            //SOF INT
	//*(U32 *) CSI_CTRL_REG1 |= 0x40000;            //RXFF int
	*(U32 *) CSI_CTRL_REG1 |= 0x80000;	//RXFF level = 8
	//*(U32 *) CSI_CTRL_REG1 |= 0x1000000;  //RXFF overflow int
	//*(U32 *) CSI_CTRL_REG2 |= 0x00100000;

	return;
}