問題：
  端口：
  input clock_a, data_a;
  input clock_b, data_b;
  output q_common;
  功能：
  clock_a上升沿時，q_common <= data_a;
  clock_b上升沿時，q_common <= data_b;
假設clock_a和clock_b不會同時出現。



法一，
module multiClock(d1, d2, clk1, clk2, q);
 input d1, d2;
 input clk1, clk2;
 output q;

 reg q1, q2;
 reg whichOne;

 always @ (posedge clk1) begin
  q1 <= d1;
 end

 always @ (posedge clk2) begin
  q2 <= d2;
 end

 always @ (clk1 or clk2) begin
  case(1)  // synthesis parallel_case
  clk1 : whichOne = 0;
  clk2 : whichOne = 1;
  endcase  // latch inferred
 end

 assign q = whichOne ? q2 : q1;

endmodule





 
 
 
 
 
法二， 
input data_a,data_b,clk_a,clk_b;
output q_common;
reg q_common;
always @(posedge clk_a or posedge clk_b)
begin
        if(clk_a) q_common=data_a;
        else      q_common=dtat_b;
end