library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(clk1,clk2:in std_logic;
a,b:in std_logic;
y:out std_logic_vector(0 to 7));
end entity;
architecture one of counter is
begin
process(clk1,clk2)
variable q1:std_logic_vector (0 to 7);
begin
if a='1' then
  if b='1' then
   if clk1'event and clk1='1' then q1:=q1+1;
   end if;
  else
   if  clk1'event and clk1='1' then q1:=q1-1;
   end if;
  end if;
else
 if b='1' then
   if clk2'event and clk2='1' then q1:=q1+1;
   end if;
  else
   if  clk2'event and clk2='1' then q1:=q1-1;
   end if;
  end if;
end if;
y<=q1;
end process;
end one;