/******************************************************************************/
/*  Copyright 2004 by SEED Electronic Technology LTD.                         */
/*  All rights reserved. SEED Electronic Technology LTD.                      */
/*  Restricted rights to use, duplicate or disclose this code are             */
/*  granted through contract.                                                 */
/******************************************************************************/
/********************************************************************************\
\*DEC6713_CODEC.c		-Codec AIC23B test programme.
\*
\*
\*
\********************************************************************************/
#include <csl.h>
#include <csl_mcbsp.h>
#include <DEC6713.h>
#include <c6x.h>
#include <codec.h>
#include <csl_edma.h>
#include <csl_irq.h>
#include <stdio.h>
#include <csl_emif.h>



//#include <config.h>
#define Ture 1
extern far void vectors();
Uint32 *Src_StartAdd;
Uint32 TempData;

int wait;
int i,a=0;
Uint32 data1[5]={1127,2328,5629,1530,6331};
Uint32 data2[5]={2132,3353,5234,3425,6636};
Uint32 edmainbuff=60;

 void init_mcbsp0(void);
 void set_interrupts_edma(void);
 
 
MCBSP_Handle hMcbsp1;
EDMA_Handle hEdma1;
EDMA_Handle hEdma2;   
EDMA_Handle hEdmaPing1; /* Handle for the ping EDMA reload parameters  */
EDMA_Handle hEdmaPong1; /* Handle for the pong EDMA reload parameters  */
EDMA_Config cfgEdma1;   /* EDMA configuration structure   */
//EDMA_Handle hEdmadummy;
 
 
EDMA_Config cfgEdmaPing1 = {  
      EDMA_OPT_RMK(
       EDMA_OPT_PRI_HIGH,
       EDMA_OPT_ESIZE_32BIT,
       EDMA_OPT_2DS_NO,
       EDMA_OPT_SUM_INC,
       EDMA_OPT_2DD_NO,
       EDMA_OPT_DUM_NONE,
       EDMA_OPT_TCINT_YES,
       EDMA_OPT_TCC_OF(12),
       EDMA_OPT_LINK_YES,
       EDMA_OPT_FS_NO
       ),
       EDMA_SRC_RMK(0x00000000),
       EDMA_CNT_RMK(0,2),
       EDMA_DST_RMK(0X00000000),
       EDMA_IDX_RMK(0,2),
       EDMA_RLD_RMK(0,0)
};  
EDMA_Config cfgEdmaPong1 = {  
      EDMA_OPT_RMK(
       EDMA_OPT_PRI_HIGH,
       EDMA_OPT_ESIZE_32BIT,
       EDMA_OPT_2DS_NO,
       EDMA_OPT_SUM_INC,
       EDMA_OPT_2DD_NO,
       EDMA_OPT_DUM_NONE,
       EDMA_OPT_TCINT_YES,
       EDMA_OPT_TCC_OF(12),
       EDMA_OPT_LINK_YES,
       EDMA_OPT_FS_NO
       ),
       EDMA_SRC_RMK(0x00000000),
       EDMA_CNT_RMK(0,5),
       EDMA_DST_RMK(0X00000000),
       EDMA_IDX_RMK(0,2),
       EDMA_RLD_RMK(0,0)
}; 
void main()
 {
     CSL_init();
     DEC6713_init();
     IRQ_setVecs(vectors);
     init_mcbsp0();
	 MCBSP_enableSrgr(hMcbsp1); 
     for(wait=0;wait<0x10;wait++);
    EDMA_clearPram(0x00000000);
     set_interrupts_edma();
     
     /**************************************************************/
     hEdma1=EDMA_open(EDMA_CHA_XEVT0,EDMA_OPEN_RESET);
     
  hEdmaPing1 = EDMA_allocTable(-1);
  hEdmaPong1 = EDMA_allocTable(-1);
 
  /* Let's copy the ping reload configuration structure to an */
  /* intermediate configuration structure.                    */
  cfgEdmaPing1.src = EDMA_SRC_RMK(data1);
  cfgEdmaPong1.src = EDMA_SRC_RMK(data2);
  cfgEdmaPing1.dst = EDMA_DST_RMK(MCBSP_ADDRH(hMcbsp1,DXR));
  cfgEdmaPong1.dst = EDMA_DST_RMK(MCBSP_ADDRH(hMcbsp1,DXR));
  /* Let's initialize the link fields of the configuration structures */
  
 
  
  cfgEdmaPing1.rld = EDMA_RLD_RMK(0,hEdmaPong1);
  cfgEdmaPong1.rld = EDMA_RLD_RMK(0,hEdmaPing1);
  cfgEdma1 = cfgEdmaPing1;
  
  
  
  /* Now let's program up the EDMA channel with the configuration structure */
  EDMA_config(hEdma1, &cfgEdma1);  
  /* Let's also configure the reload parameter tables in the EDMA PRAM  */
  /* with the values in the configuration structures.                   */
  EDMA_config(hEdmaPing1, &cfgEdmaPing1);
  EDMA_config(hEdmaPong1, &cfgEdmaPong1);  
  

 
      
      
      EDMA_enableChannel(hEdma1);
    //    EDMA_enableChannel(hEdma2);
      MCBSP_enableXmt(hMcbsp1);
    //    MCBSP_enableRcv(hMcbsp0);
  // MCBSP_enableFsync(hMcbsp0);

while(Ture)
 {
;		
}
  }
	



/********************************************************************************/
/* End of DEC6713_CODEC.C */
/********************************************************************************/

 void init_mcbsp0(void)
 {
   MCBSP_Config mcbspCfg1={
   MCBSP_SPCR_RMK(
   MCBSP_SPCR_FREE_DEFAULT,
   MCBSP_SPCR_SOFT_DEFAULT,
   MCBSP_SPCR_FRST_YES,
   MCBSP_SPCR_GRST_DEFAULT,
   MCBSP_SPCR_XINTM_XRDY,
   MCBSP_SPCR_XSYNCERR_DEFAULT,
   MCBSP_SPCR_XRST_YES,
   MCBSP_SPCR_DLB_ON,
   MCBSP_SPCR_RJUST_RZF,
   MCBSP_SPCR_CLKSTP_DEFAULT,
   MCBSP_SPCR_DXENA_ON,
   MCBSP_SPCR_RINTM_RRDY,
   MCBSP_SPCR_RSYNCERR_DEFAULT,
   MCBSP_SPCR_RRST_DEFAULT
   ),

         MCBSP_RCR_RMK(
   MCBSP_RCR_RPHASE_SINGLE,
   MCBSP_RCR_RFRLEN2_DEFAULT,
   MCBSP_RCR_RWDLEN2_DEFAULT,
   MCBSP_RCR_RCOMPAND_MSB,
   MCBSP_RCR_RFIG_YES,
   MCBSP_RCR_RDATDLY_0BIT,
   MCBSP_RCR_RFRLEN1_OF(0),
   MCBSP_RCR_RWDLEN1_32BIT,
   MCBSP_RCR_RWDREVRS_DISABLE
   ),
   
      MCBSP_XCR_RMK(
   MCBSP_XCR_XPHASE_SINGLE,
   MCBSP_XCR_XFRLEN2_DEFAULT,
   MCBSP_XCR_XWDLEN2_DEFAULT,
   MCBSP_XCR_XCOMPAND_MSB,
   MCBSP_XCR_XFIG_YES,
   MCBSP_XCR_XDATDLY_0BIT,
   MCBSP_XCR_XFRLEN1_OF(0),
   MCBSP_XCR_XWDLEN1_32BIT,
   MCBSP_XCR_XWDREVRS_DISABLE
   ),
   MCBSP_SRGR_RMK(
   MCBSP_SRGR_GSYNC_DEFAULT,
   MCBSP_SRGR_CLKSP_DEFAULT,
   MCBSP_SRGR_CLKSM_INTERNAL,
   MCBSP_SRGR_FSGM_DXR2XSR,
   MCBSP_SRGR_FPER_DEFAULT,
   MCBSP_SRGR_FWID_DEFAULT,
   MCBSP_SRGR_CLKGDV_OF(15)
   ),
   MCBSP_MCR_DEFAULT,
   MCBSP_RCER_DEFAULT,
   MCBSP_XCER_DEFAULT,
   MCBSP_PCR_RMK(
   MCBSP_PCR_XIOEN_SP,
   MCBSP_PCR_RIOEN_DEFAULT,
   MCBSP_PCR_FSXM_EXTERNAL,
   MCBSP_PCR_FSRM_EXTERNAL,
   MCBSP_PCR_CLKXM_INPUT,
   MCBSP_PCR_CLKRM_INPUT,
   MCBSP_PCR_CLKSSTAT_DEFAULT,
   MCBSP_PCR_DXSTAT_DEFAULT,
   MCBSP_PCR_FSXP_ACTIVEHIGH,
   MCBSP_PCR_FSRP_ACTIVEHIGH,
   MCBSP_PCR_CLKXP_RISING,
   MCBSP_PCR_CLKRP_FALLING
   )
   };
   hMcbsp1=MCBSP_open(MCBSP_DEV0,MCBSP_OPEN_RESET);
   MCBSP_config(hMcbsp1,&mcbspCfg1);
   
 }
 /***************************************************************/
 void set_interrupts_edma(void)
 {
   IRQ_nmiEnable();
   IRQ_globalEnable();
   IRQ_reset(IRQ_EVT_EDMAINT);
   IRQ_disable(IRQ_EVT_EDMAINT);
   EDMA_intDisable(12);
 //  EDMA_intDisable(13);
   IRQ_clear(IRQ_EVT_EDMAINT);
  EDMA_intClear(12);
  // EDMA_intClear(13);
   IRQ_enable(IRQ_EVT_EDMAINT);
  EDMA_intEnable(12);
 //  EDMA_intEnable(13);
   return;
   
 }
 
 
 interrupt void 
 c_int08()
 {
 
   EDMA_intClear(12);
 /*  a++;
  if(a%2==0)
    EDMA_link(hEdma1,hEdmaPong1);
    else
    EDMA_link(hEdma1,hEdmaPing1);  */
 }