?? f2812regs_c.h
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/*串行外設接口控制寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define SPICCR ((REGS16U)0x007040) /* SPI Config Control Reg */
#define SPICTL ((REGS16U)0x007041) /* SPI Operation Control Reg */
#define SPIST ((REGS16U)0x007042) /* SPI Status Reg */
#define SPIBRR ((REGS16U)0x007044) /* SPI Baud rate control reg */
#define SPIEMU ((REGS16U)0x007046) /* SPI Emulation buffer reg */
#define SPIRXBUF ((REGS16U)0x007047) /* SPI Serial Input buffer reg */
#define SPITXBUF ((REGS16U)0x007048) /* SPI Serial Output Buffer Register */
#define SPIDAT ((REGS16U)0x007049) /* SPI Serial Data reg */
#define SPIFFTX ((REGS16U)0x00704A) /* SPI FIFO Transmit Register */
#define SPIFFRX ((REGS16U)0x00704B) /* SPI FIFO Receive Register */
#define SPIFFCT ((REGS16U)0x00704C) /* SPI FIFO Control Register */
#define SPIPC1 ((REGS16U)0x00704D) /* SPI Port control reg1 */
#define SPIPC2 ((REGS16U)0x00704E) /* SPI Port control reg2 */
#define SPIPR1 ((REGS16U)0x00704F) /* SPI Priority control reg */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*串行通信接口A控制寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define SCICCRA ((REGS16U)0x007050) /* SCI-A Comms Control Reg */
#define SCICTL1A ((REGS16U)0x007051) /* SCI-A Control Reg 1 */
#define SCIHBAUDA ((REGS16U)0x007052) /* SCI-A Baud rate control */
#define SCILBAUDA ((REGS16U)0x007053) /* SCI-A Baud rate control */
#define SCICTL2A ((REGS16U)0x007054) /* SCI-A Control Reg 2 */
#define SCIRXSTA ((REGS16U)0x007055) /* SCI-A Receive status reg */
#define SCIRXEMUA ((REGS16U)0x007056) /* SCI-A EMU data buffer */
#define SCIRXBUFA ((REGS16U)0x007057) /* SCI-A Receive data buffer */
#define SCITXBUFA ((REGS16U)0x007059) /* SCI-A Transmit data buffer */
#define SCIFFTXA ((REGS16U)0x00705A) /* SCI-A FIFO Transmit Register */
#define SCIFFRXA ((REGS16U)0x00705B) /* SCI-A FIFO Receive Register */
#define SCIFFCTA ((REGS16U)0x00705C) /* SCI-A FIFO Control Register */
#define SCIPC1A ((REGS16U)0x00705D) /* SCI-A Port control reg1 */
#define SCIPC2A ((REGS16U)0x00705E) /* SCI-A Port control reg2 */
#define SCIPRIA ((REGS16U)0x00705F) /* SCI-A Priority control reg */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*串行通信接口B控制寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define SCICCRB ((REGS16U)0x007750) /* SCI-B Comms Control Reg */
#define SCICTL1B ((REGS16U)0x007751) /* SCI-B Control Reg 1 */
#define SCIHBAUDB ((REGS16U)0x007752) /* SCI-B Baud rate control */
#define SCILBAUDB ((REGS16U)0x007753) /* SCI-B Baud rate control */
#define SCICTL2B ((REGS16U)0x007754) /* SCI-B Control Reg 2 */
#define SCIRXSTB ((REGS16U)0x007755) /* SCI-B Receive status reg */
#define SCIRXEMUB ((REGS16U)0x007756) /* SCI-B EMU data buffer */
#define SCIRXBUFB ((REGS16U)0x007757) /* SCI-B Receive data buffer */
#define SCITXBUFB ((REGS16U)0x007759) /* SCI-B Transmit data buffer */
#define SCIFFTXB ((REGS16U)0x00775A) /* SCI-B FIFO Transmit Register */
#define SCIFFRXB ((REGS16U)0x00775B) /* SCI-B FIFO Receive Register */
#define SCIFFCTB ((REGS16U)0x00775C) /* SCI-B FIFO Control Register */
#define SCIPC1B ((REGS16U)0x00775D) /* SCI-B Port control reg1 */
#define SCIPC2B ((REGS16U)0x00775E) /* SCI-B Port control reg2 */
#define SCIPRIB ((REGS16U)0x00775F) /* SCI-B Priority control reg */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*事件管理器模塊控制寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define GPTCONA ((REGS16U)0x007400) /* General Timer Controls A */
#define T1CNT ((REGS16U)0x007401) /* T1 Counter Register */
#define T1CMPR ((REGS16U)0x007402) /* T1 Compare Register */
#define T1PR ((REGS16U)0x007403) /* T1 Period Register */
#define T1CON ((REGS16U)0x007404) /* T1 Control Register */
#define T2CNT ((REGS16U)0x007405) /* T2 Counter Register */
#define T2CMPR ((REGS16U)0x007406) /* T2 Compare Register */
#define T2PR ((REGS16U)0x007407) /* T2 Period Register */
#define T2CON ((REGS16U)0x007408) /* T2 Control Register */
#define EXTCONA ((REGS16U)0x007409) /* GP Extension Control Register A */
#define COMCONA ((REGS16U)0x007411) /* Compare Unit Control A */
#define ACTRA ((REGS16U)0x007413) /* Full Compare Unit Output Action Ctrl A */
#define DBTCONA ((REGS16U)0x007415) /* Dead Band Timer Control A */
#define CMPR1 ((REGS16U)0x007417) /* Full Compare Channel 1 Threshold */
#define CMPR2 ((REGS16U)0x007418) /* Full Compare Channel 2 Threshold */
#define CMPR3 ((REGS16U)0x007419) /* Full Compare Channel 3 Threshold */
#define CAPCONA ((REGS16U)0x007420) /* Capture Unit Control A */
#define CAPFIFOA ((REGS16U)0x007422) /* Capture FIFO Status Register A */
#define CAP1FIFO ((REGS16U)0x007423) /* Capture Channel 1 FIFO Top */
#define CAP2FIFO ((REGS16U)0x007424) /* Capture Channel 2 FIFO Top */
#define CAP3FIFO ((REGS16U)0x007425) /* Capture Channel 3 FIFO Top */
#define CAP1FBOT ((REGS16U)0x007427) /* Bottom Register Of Capture FIFO Stack 1 */
#define CAP2FBOT ((REGS16U)0x007428) /* Bottom Register Of Capture FIFO Stack 2 */
#define CAP3FBOT ((REGS16U)0x007429) /* Bottom Register Of Capture FIFO Stack 3 */
#define EVAIMRA ((REGS16U)0x00742C) /* Interrupt Mask Register A */
#define EVAIMRB ((REGS16U)0x00742D) /* Interrupt Mask Register B */
#define EVAIMRC ((REGS16U)0x00742E) /* Interrupt Mask Register C */
#define EVAIFRA ((REGS16U)0x00742F) /* Interrupt Flag Register A */
#define EVAIFRB ((REGS16U)0x007430) /* Interrupt Flag Register B */
#define EVAIFRC ((REGS16U)0x007431) /* Interrupt Flag Register C */
/*-----------------------------*/
#define GPTCONB ((REGS16U)0x007500) /* General Timer Controls B */
#define T3CNT ((REGS16U)0x007501) /* T3 Counter Register */
#define T3CMPR ((REGS16U)0x007502) /* T3 Compare Register */
#define T3PR ((REGS16U)0x007503) /* T3 Period Register */
#define T3CON ((REGS16U)0x007504) /* T3 Control Register */
#define T4CNT ((REGS16U)0x007505) /* T4 Counter Register */
#define T4CMPR ((REGS16U)0x007506) /* T4 Compare Register */
#define T4PR ((REGS16U)0x007507) /* T4 Period Register */
#define T4CON ((REGS16U)0x007508) /* T4 Control Register */
#define EXTCONB ((REGS16U)0x007509) /* GP Extension Control Register B */
#define COMCONB ((REGS16U)0x007511) /* Compare Unit Control B */
#define ACTRB ((REGS16U)0x007513) /* Full Compare Unit Output Action Ctrl B */
#define DBTCONB ((REGS16U)0x007515) /* Dead Band Timer Control B */
#define CMPR4 ((REGS16U)0x007517) /* Full Compare Channel 4 Threshold */
#define CMPR5 ((REGS16U)0x007518) /* Full Compare Channel 5 Threshold */
#define CMPR6 ((REGS16U)0x007519) /* Full Compare Channel 6 Threshold */
#define CAPCONB ((REGS16U)0x007520) /* Capture Unit Control B */
#define CAPFIFOB ((REGS16U)0x007522) /* Capture FIFO Status Register B */
#define CAP4FIFO ((REGS16U)0x007523) /* Capture Channel 4 FIFO Top */
#define CAP5FIFO ((REGS16U)0x007524) /* Capture Channel 5 FIFO Top */
#define CAP6FIFO ((REGS16U)0x007525) /* Capture Channel 6 FIFO Top */
#define CAP4FBOT ((REGS16U)0x007527) /* Bottom Register Of Capture FIFO Stack 4 */
#define CAP5FBOT ((REGS16U)0x007528) /* Bottom Register Of Capture FIFO Stack 5 */
#define CAP6FBOT ((REGS16U)0x007529) /* Bottom Register Of Capture FIFO Stack 6 */
#define EVBIMRA ((REGS16U)0x00752C) /* Interrupt Mask Register A */
#define EVBIMRB ((REGS16U)0x00752D) /* Interrupt Mask Register B */
#define EVBIMRC ((REGS16U)0x00752E) /* Interrupt Mask Register C */
#define EVBIFRA ((REGS16U)0x00752F) /* Interrupt Flag Register A */
#define EVBIFRB ((REGS16U)0x007530) /* Interrupt Flag Register B */
#define EVBIFRC ((REGS16U)0x007531) /* Interrupt Flag Register C */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*定義MCBSP寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define DRR2 ((REGS16U)0x007800) /* McBSP Data Receive Register 2 */
#define DRR1 ((REGS16U)0x007801) /* McBSP Data Receive Register 1 */
#define DXR2 ((REGS16U)0x007802) /* McBSP Data Transmit Register 2 */
#define DXR1 ((REGS16U)0x007803) /* McBSP Data Transmit Register 1 */
#define SPCR2 ((REGS16U)0x007804) /* McBSP Serial Port Control Register 2 */
#define SPCR1 ((REGS16U)0x007805) /* McBSP Serial Port Control Register 1 */
#define RCR2 ((REGS16U)0x007806) /* McBSP Receive Control Register 2 */
#define RCR1 ((REGS16U)0x007807) /* McBSP Receive Control Register 1 */
#define XCR2 ((REGS16U)0x007808) /* McBSP Transmit Control Register 2 */
#define XCR1 ((REGS16U)0x007809) /* McBSP Transmit Control Register 1 */
#define SRGR2 ((REGS16U)0x00780A) /* McBSP Sample Rate Generator Register 2 */
#define SRGR1 ((REGS16U)0x00780B) /* McBSP Sample Rate Generator Register 1 */
#define MCR2 ((REGS16U)0x00780C) /* McBSP Multichannel Register 2 */
#define MCR1 ((REGS16U)0x00780D) /* McBSP Multichannel Register 1 */
#define RCERA ((REGS16U)0x00780E) /* McBSP Receive Channel Enable Register Partition A */
#define RCERB ((REGS16U)0x00780F) /* McBSP Receive Channel Enable Register Partition B */
#define XCERA ((REGS16U)0x007810) /* McBSP Transmit Channel Enable Register Partition A */
#define XCERB ((REGS16U)0x007811) /* McBSP Transmit Channel Enable Register Partition B */
#define PCR1 ((REGS16U)0x007812) /* McBSP Pin Control Register */
#define RCERC ((REGS16U)0x007813) /* McBSP Receive Channel Enable Register Partition C */
#define RCERD ((REGS16U)0x007814) /* McBSP Receive Channel Enable Register Partition D */
#define XCERC ((REGS16U)0x007815) /* McBSP Transmit Channel Enable Register Partition C */
#define XCERD ((REGS16U)0x007816) /* McBSP Transmit Channel Enable Register Partition D */
#define RCERE ((REGS16U)0x007817) /* McBSP Receive Channel Enable Register Partition E */
#define RCERF ((REGS16U)0x007818) /* McBSP Receive Channel Enable Register Partition F */
#define XCERE ((REGS16U)0x007819) /* McBSP Transmit Channel Enable Register Partition E */
#define XCERF ((REGS16U)0x00781A) /* McBSP Transmit Channel Enable Register Partition F */
#define RCERG ((REGS16U)0x00781B) /* McBSP Receive Channel Enable Register Partition G */
#define RCERH ((REGS16U)0x00781C) /* McBSP Receive Channel Enable Register Partition H */
#define XCERG ((REGS16U)0x00781D) /* McBSP Transmit Channel Enable Register Partition G */
#define XCERH ((REGS16U)0x00781E) /* McBSP Transmit Channel Enable Register Partition H */
#define MFFTX ((REGS16U)0x007820) /* McBSP Transmit FIFO Register */
#define MFFRX ((REGS16U)0x007821) /* McBSP Receive FIFO Register */
#define MFFCT ((REGS16U)0x007822) /* McBSP FIFO Control Register */
#define MFFINT ((REGS16U)0x007823) /* McBSP FIFO Interrupt Register */
#define MFFST ((REGS16U)0x007824) /* McBSP FIFO Status Register */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#endif
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
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