#define 	MMCSDR_BASE				0xF0214000#endif#ifdef CONFIG_ARCH_MX2ADS#define		MMCSDR_BASE				IO_ADDRESS(0x10013000)#define		MMCSDR_BASE_2			IO_ADDRESS(0x10014000)//for SD2 #endif#define 	MMCSDR_STR_STP_CLK		(MMCSDR_BASE)	#define 	MMCSDR_STATUS 			(MMCSDR_BASE+0x4)	#define  	MMCSDR_CLK_RATE			(MMCSDR_BASE+0x8)	#define 	MMCSDR_CMD_DAT_CONT   	(MMCSDR_BASE+0xC)	#define 	MMCSDR_RES_TO			(MMCSDR_BASE+0x10)	#define 	MMCSDR_READ_TO			(MMCSDR_BASE+0x14)	#define 	MMCSDR_BLK_LEN			(MMCSDR_BASE+0x18)	#define 	MMCSDR_NOB				(MMCSDR_BASE+0x1C)	#define 	MMCSDR_REV_NO			(MMCSDR_BASE+0x20)	#define 	MMCSDR_INT_MASK			(MMCSDR_BASE+0x24)	#define 	MMCSDR_CMD				(MMCSDR_BASE+0x28)#define 	MMCSDR_ARGUMENTH		(MMCSDR_BASE+0x2C)	#define 	MMCSDR_ARGUMENTL		(MMCSDR_BASE+0x30)	#define 	MMCSDR_RES_FIFO			(MMCSDR_BASE+0x34)	#define 	MMCSDR_BUFFER_ACCESS	(MMCSDR_BASE+0x38)	#define		MMCSDR_BUF_PART_FULL	(MMCSDR_BASE+0x3c)	#define mmcsdr_str_stp_clk     	(*((volatile unsigned long *)(MMCSDR_STR_STP_CLK)))#define mmcsdr_status     		(*((volatile unsigned long *)(MMCSDR_STATUS)))#define mmcsdr_clk_rate     	(*((volatile unsigned long *)(MMCSDR_CLK_RATE)))#define mmcsdr_cmd_dat_cont     (*((volatile unsigned long *)(MMCSDR_CMD_DAT_CONT)))#define mmcsdr_res_to     		(*((volatile unsigned long *)(MMCSDR_RES_TO)))#define mmcsdr_read_to     		(*((volatile unsigned long *)(MMCSDR_READ_TO)))#define mmcsdr_blk_len     		(*((volatile unsigned long *)(MMCSDR_BLK_LEN)))#define mmcsdr_nob     			(*((volatile unsigned long *)(MMCSDR_NOB)))#define mmcsdr_rev_no     		(*((volatile unsigned long *)(MMCSDR_REV_NO)))#define mmcsdr_int_mask     	(*((volatile unsigned long *)(MMCSDR_INT_MASK)))#define mmcsdr_cmd     			(*((volatile unsigned long *)(MMCSDR_CMD)))#define mmcsdr_argumenth     	(*((volatile unsigned long *)(MMCSDR_ARGUMENTH)))#define mmcsdr_argumentl     	(*((volatile unsigned long *)(MMCSDR_ARGUMENTL)))#define mmcsdr_res_fifo     	(*((volatile unsigned long *)(MMCSDR_RES_FIFO)))#define mmcsdr_buffer_access    (*((volatile unsigned long *)(MMCSDR_BUFFER_ACCESS)))#ifdef CONFIG_ARCH_MX2ADS#define 	MMCSDR_STR_STP_CLK_2		(MMCSDR_BASE_2)	#define 	MMCSDR_STATUS_2 			(MMCSDR_BASE_2+0x4)	#define  	MMCSDR_CLK_RATE_2			(MMCSDR_BASE_2+0x8)	#define 	MMCSDR_CMD_DAT_CONT_2   	(MMCSDR_BASE_2+0xC)	#define 	MMCSDR_RES_TO_2				(MMCSDR_BASE_2+0x10)	#define 	MMCSDR_READ_TO_2			(MMCSDR_BASE_2+0x14)	#define 	MMCSDR_BLK_LEN_2			(MMCSDR_BASE_2+0x18)	#define 	MMCSDR_NOB_2				(MMCSDR_BASE_2+0x1C)	#define 	MMCSDR_REV_NO_2				(MMCSDR_BASE_2+0x20)	#define 	MMCSDR_INT_MASK_2			(MMCSDR_BASE_2+0x24)	#define 	MMCSDR_CMD_2				(MMCSDR_BASE_2+0x28)#define 	MMCSDR_ARGUMENTH_2			(MMCSDR_BASE_2+0x2C)	#define 	MMCSDR_ARGUMENTL_2			(MMCSDR_BASE_2+0x30)	#define 	MMCSDR_RES_FIFO_2			(MMCSDR_BASE_2+0x34)	#define 	MMCSDR_BUFFER_ACCESS_2		(MMCSDR_BASE_2+0x38)	#define mmcsdr_str_stp_clk_2     	(*((volatile unsigned long *)(MMCSDR_STR_STP_CLK_2)))#define mmcsdr_status_2     		(*((volatile unsigned long *)(MMCSDR_STATUS_2)))#define mmcsdr_clk_rate_2     		(*((volatile unsigned long *)(MMCSDR_CLK_RATE_2)))#define mmcsdr_cmd_dat_cont_2     	(*((volatile unsigned long *)(MMCSDR_CMD_DAT_CONT_2)))#define mmcsdr_res_to_2     		(*((volatile unsigned long *)(MMCSDR_RES_TO_2)))#define mmcsdr_read_to_2     		(*((volatile unsigned long *)(MMCSDR_READ_TO_2)))#define mmcsdr_blk_len_2     		(*((volatile unsigned long *)(MMCSDR_BLK_LEN_2)))#define mmcsdr_nob_2     			(*((volatile unsigned long *)(MMCSDR_NOB_2)))#define mmcsdr_rev_no_2     		(*((volatile unsigned long *)(MMCSDR_REV_NO_2)))#define mmcsdr_int_mask_2     		(*((volatile unsigned long *)(MMCSDR_INT_MASK_2)))#define mmcsdr_cmd_2     			(*((volatile unsigned long *)(MMCSDR_CMD_2)))#define mmcsdr_argumenth_2     		(*((volatile unsigned long *)(MMCSDR_ARGUMENTH_2)))#define mmcsdr_argumentl_2     		(*((volatile unsigned long *)(MMCSDR_ARGUMENTL_2)))#define mmcsdr_res_fifo_2     		(*((volatile unsigned long *)(MMCSDR_RES_FIFO_2)))#define mmcsdr_buffer_access_2    	(*((volatile unsigned long *)(MMCSDR_BUFFER_ACCESS_2)))#endif#define		MMCSDB_R1			0x01#define 	MMCSDB_R2			0x02#define 	MMCSDB_R3			0x03#define 	MMCSDB_R5			0x05#define		MMCSDB_DATEN		0x08#define		MMCSDB_WRRD			0x10#define		MMCSDB_STRBLK		0x20#define		MMCSDB_BSY			0x40#define		MMCSDB_INIT			0x80#define 	MMCSD_BUS_4BIT		0x200/*-------------------- Mask Definitions --------------------------------------*/#define 	MMCSD_CLOCK_MASK	0x0000003/*--------------------Finish wait condition--------------------------------------*/#define     MMCSD_CMD_DONE          	0x01#define     MMCSD_DATA_TRANS_DONE   	0x02/*--------------------------------------------------------------------------*//*               ILLEGAL ERRORS THAT SOFTWARE CHECKS                        *//*--------------------------------------------------------------------------*/#define    MMCSD_CSD_MISS                 0x1000/* ABNORMAL CSD               */#define    MMCSD_CID_MISS                 0x2000/* ABNORMAL CID               */#define    MMCSD_MBR_ERROR                0x3000/* ABNORMAL MBR DATA          */#define    MMCSD_BPB_ERROR                0x4000/* ABNORMAL BPB DATA          */#define    MMCSD_NO_CARD                  0x5000/* CANNOT IDENTIFY CARD       */#define    MMCSD_NOT_EXIST_AREA           0x6000/* ACCESS TO NON-EXIST DOMAIN */#define    MMCSD_ILLEGAL_STATE            0x7000#define    MMCSD_ILLEGAL_ERROR_MASK                               0xF000#define    MMCSD_STATUS_NOERROR    0xFDFF0000#define		MMCSD_READ_TIMEOUT 0x1 //fix#define		MMCSD_CMD_TIMEOUT  0x2 //fix with MMC status register. CMD error#define		MMCSD_WRITE_CRC    0x4 //fix#define		MMCSD_READ_CRC     0x8 //fix#define		MMCSD_HARDWARE_REV 0x10#define		MMCSD_RESP_CRC_ERR  0x20 //fix with MMC status register. CMD error#define		MMCSD_CARD_BUSY    0x200  //only use in CMD1#define		MMCSD_END_CMD_RESP 0x2000#define		MMCSD_STATUS_ERR  (MMCSD_READ_TIMEOUT|MMCSD_CMD_TIMEOUT|MMCSD_WRITE_CRC)//#define		MMCSD_STATUS_ERR  (MMCSD_READ_TIMEOUT|MMCSD_CMD_TIMEOUT|MMCSD_WRITE_CRC|MMCSD_RESP_CRC_ERR)#define		MMCSD_STATUS 	u32#define  	MMCSD_ADP_REPEATNUM     1500    /* Define retry times*/#define  	MMCSD_MMC_CARD_VOLTAGE    0x00ff8000#define  	MMCSD_CARD_VOLTAGE    0x00ff8000#define  	MMCSD_CARD_SET_VOLTAGE    0x00008000/*--------------------------------------------------------------------------*//*               Pin Configuration		                            *//*--------------------------------------------------------------------------*/#ifndef CONFIG_ARCH_MX2ADS#define DBMX1_GIUS_B	0xf021c120#define DBMX1_GPR_B	0xf021c138#define DBMX1_PUEN_B	0xf021c140#define DBMX1_DDIR_B	0xf021c100#define DBMX1_OCR1_B	0xf021c104#define DBMX1_DR_B	0xf021c11c#define DBMX1_IMR_B	0xf021c130#define DBMX1_ICR2_B	0xf021c12c#define DBMX1_ISR_B	0xf021c134#define AIPI2_BASE_ADDR         0xF0210000             #define AIPI2_PSR0              AIPI2_BASE_ADDR        // ; Peripheral Size Reg 0#define AIPI2_PSR1              (AIPI2_BASE_ADDR+0x04)  // ; Peripheral Size Reg 1#define AIPI2_PAR               (AIPI2_BASE_ADDR+0x08)  // ; Peripheral Access Reg#define CRM_BASE_ADDR           0xF021B000                #define CRM_CSCR                CRM_BASE_ADDR           // ; Clock Source Control Reg#define CRM_MPCTL0              (CRM_BASE_ADDR+0x04)    // ; MCU PLL Control Reg      #define CRM_MPCTL1              (CRM_BASE_ADDR+0x08)  // ; MCU PLL & System Clk Ctl Reg#define CRM_UPCTL0              (CRM_BASE_ADDR+0x0C)    // ; USB PLL Control Reg 0#define CRM_UPCTL1              (CRM_BASE_ADDR+0x10)    // ; USB PLL Control Reg 1#define CRM_PCDR                (CRM_BASE_ADDR+0x20)  // ; Perpheral Clock Divider Reg#define CRM_RSR                 (CRM_BASE_ADDR+0x800)   // ; Reset Source Reg #define CRM_SIDR                (CRM_BASE_ADDR+0x804)   // ; Silicon ID Reg #define CRM_FMCR                (CRM_BASE_ADDR+0x808)   // ; Functional Muxing Control Reg #define CRM_GPCR                (CRM_BASE_ADDR+0x80C)   // ; Global Control Reg #define PLL_BASE                0xF021B000/* Reset Module*/#define PLL_CSCR                (PLL_BASE+0x00) //Clock Source Control Register#define PLL_PCDR                (PLL_BASE+0x20) //Peripherial Clock Divider Register/* PLL & Clock Controller */#define PLL_MCTL0               (PLL_BASE+0x04) //MCU PLL Control Register 0#define PLL_MCTL1               (PLL_BASE+0x08) //MCU PLL Control Register 1#define PLL_UPCTL0              (PLL_BASE+0x0C) //USB PLL Control Register 0#define PLL_UPCTL1              (PLL_BASE+0x10) //USB PLL Control Register 1/* System Control */#define PLL_RSR                 (PLL_BASE+0x800) //Reset Source Register#define PLL_SIDR                (PLL_BASE+0x804) //Silicon ID Register#define PLL_FMCR                (PLL_BASE+0x808) //Function Muxing Control Register#define PLL_GPCR                (PLL_BASE+0x80C) //Global Peripherial Control Regiser#else	//for MX21#endif#endif