?? delay.pin
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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
---------------------------------------------------------------------------------
Quartus II Version 6.0 Build 178 04/27/2006 SJ Full Version
CHIP "delay" ASSIGNED TO AN: EP2C5T144C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : LVTTL : : 1 : N
Dout[3] : 3 : output : LVTTL : : 1 : N
GND* : 4 : : : : 1 :
VCCIO1 : 5 : power : : 3.3V : 1 :
GND : 6 : gnd : : : :
GND* : 7 : : : : 1 :
GND* : 8 : : : : 1 :
GND* : 9 : : : : 1 :
TDO : 10 : output : : : 1 :
TMS : 11 : input : : : 1 :
TCK : 12 : input : : : 1 :
TDI : 13 : input : : : 1 :
DATA0 : 14 : input : : : 1 :
DCLK : 15 : : : : 1 :
nCE : 16 : : : : 1 :
clk : 17 : input : LVTTL : : 1 : N
rst : 18 : input : LVTTL : : 1 : N
GND : 19 : gnd : : : :
nCONFIG : 20 : : : : 1 :
GND+ : 21 : : : : 1 :
GND+ : 22 : : : : 1 :
VCCIO1 : 23 : power : : 3.3V : 1 :
GND* : 24 : : : : 1 :
GND* : 25 : : : : 1 :
Dout[5] : 26 : output : LVTTL : : 1 : N
GND* : 27 : : : : 1 :
GND* : 28 : : : : 1 :
VCCIO1 : 29 : power : : 3.3V : 1 :
GND* : 30 : : : : 1 :
Dout[2] : 31 : output : LVTTL : : 1 : N
GND* : 32 : : : : 1 :
GND : 33 : gnd : : : :
GND_PLL1 : 34 : gnd : : : :
VCCD_PLL1 : 35 : power : : 1.2V : :
GND_PLL1 : 36 : gnd : : : :
VCCA_PLL1 : 37 : power : : 1.2V : :
GNDA_PLL1 : 38 : gnd : : : :
GND : 39 : gnd : : : :
GND* : 40 : : : : 4 :
GND* : 41 : : : : 4 :
Din[2] : 42 : input : LVTTL : : 4 : N
GND* : 43 : : : : 4 :
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