module de(in,out,clr_n,clk);
input clk;
input clr_n;
input [7:0] in;
output[7:0] out;
reg [7:0] out;
always @(posedge clk or negedge clr_n)
begin
  if(clr_n==0)
    out<=0;
  else out<=in;
end
endmodule
module delay(Din,Dout,clk,rst);
input [7:0] Din;
input clk,rst;
output [7:0] Dout;
//wire Dout;
wire [7:0]out1;
wire [7:0]out2;
wire [7:0]out3;
wire [7:0]out4;
wire [7:0]out5;
wire [7:0]out6;
wire [7:0]out7;
wire [7:0]out8;
de (.in(Din),.out(out1),.clr_n(rst),.clk(clk));
de (.in(out1),.out(out2),.clr_n(rst),.clk(clk));
de (.in(out2),.out(out3),.clr_n(rst),.clk(clk));
de (.in(out3),.out(out4),.clr_n(rst),.clk(clk));
de (.in(out4),.out(out5),.clr_n(rst),.clk(clk));
de (.in(out5),.out(out6),.clr_n(rst),.clk(clk));
de (.in(out6),.out(out7),.clr_n(rst),.clk(clk));
de (.in(out7),.out(out8),.clr_n(rst),.clk(clk));
de (.in(out8),.out(Dout),.clr_n(rst),.clk(clk));
endmodule