;===========================================
; NAME: OPTION.A
; DESC: Configuration options for .S files
; HISTORY:
; 02.28.2002: ver 0.0
;===========================================

;Start address of each stacks,
_STACK_BASEADDRESS	EQU 0x33ff8000  
_MMUTT_STARTADDRESS	EQU 0x33ff8000  
_ISR_STARTADDRESS	EQU 0x33ffff00


;=================
; ISR
;=================
pISR_RESET     EQU  (_ISR_STARTADDRESS+0x0)
pISR_UNDEF     EQU  (_ISR_STARTADDRESS+0x4)
pISR_SWI       EQU  (_ISR_STARTADDRESS+0x8)
pISR_PABORT    EQU  (_ISR_STARTADDRESS+0xc)
pISR_DABORT    EQU  (_ISR_STARTADDRESS+0x10)
pISR_RESERVED  EQU  (_ISR_STARTADDRESS+0x14)
pISR_IRQ       EQU  (_ISR_STARTADDRESS+0x18)
pISR_FIQ       EQU  (_ISR_STARTADDRESS+0x1c)

pISR_EINT0     EQU  (_ISR_STARTADDRESS+0x20)
pISR_EINT1     EQU  (_ISR_STARTADDRESS+0x24)
pISR_EINT2     EQU  (_ISR_STARTADDRESS+0x28)
pISR_EINT3     EQU  (_ISR_STARTADDRESS+0x2c)
pISR_EINT4_7   EQU  (_ISR_STARTADDRESS+0x30)
pISR_EINT8_23  EQU  (_ISR_STARTADDRESS+0x34)
pISR_NOTUSED6  EQU  (_ISR_STARTADDRESS+0x38)
pISR_BAT_FLT   EQU  (_ISR_STARTADDRESS+0x3c)
pISR_TICK      EQU  (_ISR_STARTADDRESS+0x40)
pISR_WDT       EQU  (_ISR_STARTADDRESS+0x44)
pISR_TIMER0    EQU  (_ISR_STARTADDRESS+0x48)
pISR_TIMER1    EQU  (_ISR_STARTADDRESS+0x4c)
pISR_TIMER2    EQU  (_ISR_STARTADDRESS+0x50)
pISR_TIMER3    EQU  (_ISR_STARTADDRESS+0x54)
pISR_TIMER4    EQU  (_ISR_STARTADDRESS+0x58)
pISR_UART2     EQU  (_ISR_STARTADDRESS+0x5c)
pISR_LCD       EQU  (_ISR_STARTADDRESS+0x60)
pISR_DMA0      EQU  (_ISR_STARTADDRESS+0x64)
pISR_DMA1      EQU  (_ISR_STARTADDRESS+0x68)
pISR_DMA2      EQU  (_ISR_STARTADDRESS+0x6c)
pISR_DMA3      EQU  (_ISR_STARTADDRESS+0x70)
pISR_SDI       EQU  (_ISR_STARTADDRESS+0x74)
pISR_SPI0      EQU  (_ISR_STARTADDRESS+0x78)
pISR_UART1     EQU  (_ISR_STARTADDRESS+0x7c)
pISR_NOTUSED24 EQU  (_ISR_STARTADDRESS+0x80)
pISR_USBD      EQU  (_ISR_STARTADDRESS+0x84)
pISR_USBH      EQU  (_ISR_STARTADDRESS+0x88)
pISR_IIC       EQU  (_ISR_STARTADDRESS+0x8c)
pISR_UART0     EQU  (_ISR_STARTADDRESS+0x90)
pISR_SPI1      EQU  (_ISR_STARTADDRESS+0x94)
pISR_RTC       EQU  (_ISR_STARTADDRESS+0x98)
pISR_ADC       EQU  (_ISR_STARTADDRESS+0xa0)


	GBLL 	PLL_ON_START  
PLL_ON_START	SETL 	{TRUE}


	GBLL	ENDIAN_CHANGE
ENDIAN_CHANGE	SETL	{FALSE}

	GBLA	ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH	SETA	16	


;BUSWIDTH = 16,32
	

	GBLA	FCLK
FCLK		SETA	50000000

    [	FCLK = 20000000	
M_MDIV	EQU	0x20	;Fin=12.0MHz Fout=30.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 30000000	
M_MDIV	EQU	0x34	;Fin=12.0MHz Fout=30.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 50000000	
M_MDIV	EQU	0x5c	;Fin=12.0MHz Fout=50.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 60000000	
M_MDIV	EQU	0x70	;Fin=12.0MHz Fout=60.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 70000000	
M_MDIV	EQU	0x84	;Fin=12.0MHz Fout=70.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 75000000	
M_MDIV	EQU	0x8e	;Fin=12.0MHz Fout=75.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

	END