# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		VGAROM_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:47:03  SEPTEMBER 12, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_222 -to hs
set_location_assignment PIN_219 -to vs
set_location_assignment PIN_226 -to r
set_location_assignment PIN_225 -to g
set_location_assignment PIN_223 -to b
set_location_assignment PIN_2 -to A18
set_location_assignment PIN_1 -to OE1
set_location_assignment PIN_224 -to oe
set_location_assignment PIN_178 -to CLK1
set_location_assignment PIN_28 -to clk
set_location_assignment PIN_233 -to modf
set_location_assignment PIN_173 -to addr\[17\]
set_location_assignment PIN_4 -to addr\[8\]
set_location_assignment PIN_6 -to addr\[9\]
set_location_assignment PIN_7 -to addr\[11\]
set_location_assignment PIN_12 -to addr\[10\]
set_location_assignment PIN_8 -to addr\[12\]
set_location_assignment PIN_3 -to addr\[16\]
set_location_assignment PIN_168 -to addr\[15\]
set_location_assignment PIN_167 -to addr\[14\]
set_location_assignment PIN_166 -to addr\[13\]
set_location_assignment PIN_160 -to addr\[7\]
set_location_assignment PIN_159 -to addr\[6\]
set_location_assignment PIN_158 -to addr\[5\]
set_location_assignment PIN_141 -to addr\[4\]
set_location_assignment PIN_140 -to addr\[3\]
set_location_assignment PIN_139 -to addr\[2\]
set_location_assignment PIN_138 -to addr\[1\]
set_location_assignment PIN_137 -to addr\[0\]
set_location_assignment PIN_21 -to data8\[0\]
set_location_assignment PIN_41 -to data8\[1\]
set_location_assignment PIN_128 -to data8\[2\]
set_location_assignment PIN_132 -to data8\[3\]
set_location_assignment PIN_133 -to data8\[4\]
set_location_assignment PIN_134 -to data8\[5\]
set_location_assignment PIN_135 -to data8\[6\]
set_location_assignment PIN_136 -to data8\[7\]

# Timing Assignments
# ==================
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name AUTO_LCELL_INSERTION ON
set_global_assignment -name TOP_LEVEL_ENTITY vgarom

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V

# Timing Analysis Assignments
# ===========================
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS

# Assembler Assignments
# =====================
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1PC8
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC1PC8
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE ON

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME 0.0ns
set_global_assignment -name GLITCH_INTERVAL 0.0ns
set_global_assignment -name END_TIME 20.0ms

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------