?? os_cpu_a.lst
字號:
ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
3 00000000 ; The Real-Time
Kernel
4 00000000 ;
5 00000000 ; (c) Copyright 1992-2005,
Micrium, Weston, FL
6 00000000 ; All Rights Re
served
7 00000000 ;
8 00000000 ; Generic ARM
Port
9 00000000 ;
10 00000000 ; File : OS_CPU_A.ASM
11 00000000 ; Version : V1.61
12 00000000 ; By : Jean J. Labrosse
13 00000000 ;
14 00000000 ; For : ARM7 or ARM9
15 00000000 ; Mode : ARM or Thumb
16 00000000 ; Toolchain : IAR's EWARM V4.11a and higher
17 00000000 ;*******************************************************
*************************************************
18 00000000
19 00000000 IMPORT OSRunning ; IMPORTal referenc
es
20 00000000 IMPORT OSPrioCur
21 00000000 IMPORT OSPrioHighRdy
22 00000000 IMPORT OSTCBCur
23 00000000 IMPORT OSTCBHighRdy
24 00000000 IMPORT OSIntNesting
25 00000000 IMPORT OSIntExit
26 00000000 IMPORT OSTaskSwHook
27 00000000 IMPORT Timer0_Exception
28 00000000
29 00000000
30 00000000 EXPORT OS_CPU_SR_Save ; Functions decl
ared in this file
31 00000000 EXPORT OS_CPU_SR_Restore
32 00000000 EXPORT OSStartHighRdy
33 00000000 EXPORT OSCtxSw
34 00000000 EXPORT OSIntCtxSw
35 00000000 EXPORT OS_CPU_IRQ_ISR
36 00000000
37 00000000
38 00000000 000000C0
NO_INT EQU 0xC0 ; Mask used to disa
ble interrupts (Bot
h FIR and IRQ)
39 00000000 00000013
SVC32_MODE
EQU 0x13
40 00000000 00000011
FIQ32_MODE
EQU 0x11
41 00000000 00000012
IRQ32_MODE
EQU 0x12
ARM Macro Assembler Page 2
42 00000000
43 00000000 ;*******************************************************
**************************************************
44 00000000 ; CRITICAL SECTION MET
HOD 3 FUNCTIONS
45 00000000 ;
46 00000000 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
47 00000000 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
48 00000000 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II's functions that need to
49 00000000 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
50 00000000 ; into the CPU's status register.
51 00000000 ;
52 00000000 ; Prototypes : OS_CPU_SR OS_CPU_SR_Save(void);
53 00000000 ; void OS_CPU_SR_Restore(OS_CPU_S
R cpu_sr);
54 00000000 ;
55 00000000 ;
56 00000000 ; Note(s) : 1) These functions are used in general li
ke this:
57 00000000 ;
58 00000000 ; void Task (void *p_arg)
59 00000000 ; {
60 00000000 ; #if OS_CRITICAL_METHOD == 3 /
* Allocate storage for CPU status register */
61 00000000 ; OS_CPU_SR cpu_sr;
62 00000000 ; #endif
63 00000000 ;
64 00000000 ; :
65 00000000 ; :
66 00000000 ; OS_ENTER_CRITICAL(); /
* cpu_sr = OS_CPU_SaveSR(); */
67 00000000 ; :
68 00000000 ; :
69 00000000 ; OS_EXIT_CRITICAL(); /
* OS_CPU_RestoreSR(cpu_sr); */
70 00000000 ; :
71 00000000 ; :
72 00000000 ; }
73 00000000 ;
74 00000000 ; 2) OS_CPU_SaveSR() is implemented as reco
mmended by Atmel's application note:
75 00000000 ;
76 00000000 ; "Disabling Interrupts at Processor
Level"
77 00000000 ;*******************************************************
**************************************************
78 00000000
79 00000000 PRESERVE8
80 00000000 AREA OS_CPU_SR_CODE32, CODE, READONL
Y
81 00000000 ARM
82 00000000
83 00000000 OS_CPU_SR_Save
84 00000000 E10F0000 MRS R0,CPSR ; Set IRQ and FIQ b
its in CPSR to disa
ARM Macro Assembler Page 3
ble all interrupts
85 00000004 E38010C0 ORR R1,R0,#NO_INT
86 00000008 E121F001 MSR CPSR_c,R1
87 0000000C E10F1000 MRS R1,CPSR ; Confirm that CPSR
contains the prope
r interrupt disable
flags
88 00000010 E20110C0 AND R1,R1,#NO_INT
89 00000014 E35100C0 CMP R1,#NO_INT
90 00000018 1AFFFFFE BNE OS_CPU_SR_Save ; Not properly d
isabled (try again)
91 0000001C E12FFF1E BX LR ; Disabled, return
the original CPSR c
ontents in R0
92 00000020
93 00000020
94 00000020 OS_CPU_SR_Restore
95 00000020 E121F000 MSR CPSR_c,R0
96 00000024 E12FFF1E BX LR
97 00000028
98 00000028
99 00000028 ;*******************************************************
**************************************************
100 00000028 ; START MULTITA
SKING
101 00000028 ; void OSStartHigh
Rdy(void)
102 00000028 ;
103 00000028 ; Note(s) : 1) OSStartHighRdy() MUST:
104 00000028 ; a) Call OSTaskSwHook() then,
105 00000028 ; b) Set OSRunning to TRUE,
106 00000028 ; c) Switch to the highest priority task.
107 00000028 ;*******************************************************
**************************************************
108 00000028
109 00000028 AREA OSStartHighRdy_CODE32, CODE, RE
ADONLY
110 00000000 ARM
111 00000000
112 00000000 OSStartHighRdy
113 00000000
114 00000000 E51F0008 LDR R0, OS_TaskSwHook
; OSTaskSwHook();
115 00000004 E1A0E00F MOV LR, PC
116 00000008 E12FFF10 BX R0
117 0000000C
118 0000000C E32FF0D3 MSR CPSR_cxsf, #0xD3 ; Switch to SV
C mode with IRQ and
FIQ disabled
119 00000010
120 00000010 E51F4008 LDR R4, OS_Running
; OSRunning = TRUE
121 00000014 E3A05001 MOV R5, #1
122 00000018 E5C45000 STRB R5, [R4]
123 0000001C
124 0000001C ; SWITCH TO HIGHEST PRIORITY TASK
125 0000001C E51F4008 LDR R4, OS_TCBHighRdy ; Get high
est priority task T
ARM Macro Assembler Page 4
CB address
126 00000020 E5944000 LDR R4, [R4] ; get stack poin
ter
127 00000024 E594D000 LDR SP, [R4] ; switch to the
new stack
128 00000028
129 00000028 E49D4004 LDR R4, [SP], #4 ; pop new task
's CPSR
130 0000002C E16FF004 MSR SPSR_cxsf,R4
131 00000030 E8FDDFFF LDMFD SP!, {R0-R12,LR,PC}^ ; pop n
ew task's context
132 00000034
133 00000034
134 00000034 ;*******************************************************
**************************************************
135 00000034 ; PERFORM A CONTEXT SWITCH (From
task level) - OSCtxSw()
136 00000034 ;
137 00000034 ; Note(s) : 1) OSCtxSw() is called in SYS mode with BOTH
FIQ and IRQ interrupts DISABLED
138 00000034 ;
139 00000034 ; 2) The pseudo-code for OSCtxSw() is:
140 00000034 ; a) Save the current task's context onto t
he current task's stack
141 00000034 ; b) OSTCBCur->OSTCBStkPtr = SP;
142 00000034 ; c) OSTaskSwHook();
143 00000034 ; d) OSPrioCur = OSPrioHighRdy;
144 00000034 ; e) OSTCBCur = OSTCBHighRdy;
145 00000034 ; f) SP = OSTCBHighRdy->
OSTCBStkPtr;
146 00000034 ; g) Restore the new task's context from th
e new task's stack
147 00000034 ; h) Return to new task's code
148 00000034 ;
149 00000034 ; 3) Upon entry:
150 00000034 ; OSTCBCur points to the OS_TCB of the
task to suspend
151 00000034 ; OSTCBHighRdy points to the OS_TCB of the
task to resume
152 00000034 ;*******************************************************
**************************************************
153 00000034
154 00000034 AREA OSCtxSw_CODE32, CODE, READONLY
155 00000000 ARM
156 00000000
157 00000000 OSCtxSw
158 00000000 ; SAVE CURRENT TASK'S CONTEXT
159 00000000 E92D4000 STMFD SP!, {LR} ; Push return a
ddress
160 00000004 E92D4000 STMFD SP!, {LR}
161 00000008 E92D1FFF STMFD SP!, {R0-R12} ; Push regist
ers
162 0000000C E10F4000 MRS R4, CPSR ; Push current
CPSR
163 00000010 E31E0001 TST LR, #1 ; See if called
from Thumb mode
164 00000014 13844020 ORRNE R4, R4, #0x20 ; If yes, Se
t the T-bit
ARM Macro Assembler Page 5
165 00000018 E92D0010 STMFD SP!, {R4}
166 0000001C
167 0000001C E51F4008 LDR R4, OS_TCBCur ; OSTCBCur->OSTCB
StkPtr = SP;
168 00000020 E5945000 LDR R5, [R4]
169 00000024 E585D000 STR SP, [R5]
170 00000028
171 00000028 E51F0008 LDR R0, OS_TaskSwHook
; OSTaskSwHook();
172 0000002C E1A0E00F MOV LR, PC
173 00000030 E12FFF10 BX R0
174 00000034
175 00000034 E51F4008 LDR R4, OS_PrioCur ; OSPrioCur = OS
PrioHighRdy
176 00000038 E51F5008 LDR R5, OS_PrioHighRdy
177 0000003C E5D56000 LDRB R6, [R5]
178 00000040 E5C46000 STRB R6, [R4]
179 00000044
180 00000044 E51F4008 LDR R4, OS_TCBCur ; OSTCBCur = OST
CBHighRdy;
181 00000048 E51F6008 LDR R6, OS_TCBHighRdy
182 0000004C E5966000 LDR R6, [R6]
183 00000050 E5846000 STR R6, [R4]
184 00000054
185 00000054 E596D000 LDR SP, [R6] ; SP = OSTCBHighRdy
->OSTCBStkPtr;
186 00000058
?? 快捷鍵說明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -