SD-SDI reference design v1.1 readme.txtThis file contains the following sections:o  Package Contentso  Tool Requirementso  Core Directory Nameso  Release Historyo  Contacting AlteraPackage Contents================SD-SDI reference design v1.1Tool Requirements=====================This reference design requires a Verilog HDL simulator (e.g. Modelsim Altera Edition version 5.7c)Please contact your local sales representative if you do not have one of thesesoftware tools.Core Directory Names====================The default directory for your reference design is c:\altera\reference_designs,but you can specify an alternative directory. Release History===============Version 1.1-------------- Update design to use on-board VCXO in loopback mode- Quartus project support for CVDB rev 1.1 (production version)- Application note "an356" rev 1.1Contacting Altera=================Although we have made every effort to ensure that this version of thereference design works correctly, there may be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the user guide, please contactyour Altera Field Applications Engineer.If you have additional questions that are not answered in the documentationprovided with this function, contact Altera Applications using one of thefollowing methods:Technical Support Hotline:	(800) 800-EPLD (U.S.)				(408) 544-7000 (Internationally)World wide web: 		http://www.altera.com/mysupportLast updated May, 2004Copyright