/* * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> * Gary Jennejohn <gj@denx.de> * David Mueller <d.mueller@elsoft.ch> * * Configuation settings for the SAMSUNG SMDK2410 board. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef __CONFIG_H#define __CONFIG_H/* * High Level Configuration Options * (easy to change) */#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */#define CONFIG_SMDK2410		1	/* on a SAMSUNG SMDK2410 Board  *//* input clock of PLL */#define CONFIG_SYS_CLK_FREQ	12000000/* the SMDK2410 has 12MHz input clock */#define USE_920T_MMU		1#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff *//* * Size of malloc() pool */#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + (128)*1024)#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data *//* * Hardware drivers */#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */#define CS8900_BASE		0x19000300#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts *//* * select serial console configuration */#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK2410 *//************************************************************ * RTC ************************************************************/#define	CONFIG_RTC_S3C24X0	1/* allow to overwrite serial and ethaddr */#define CONFIG_ENV_OVERWRITE#define CONFIG_BAUDRATE		115200/*********************************************************** * Command definition ***********************************************************//* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port *//* what's this ? it's not used anywhere */#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */#endif/* * Miscellaneous configurable options */#define	CFG_LONGHELP				/* undef to save memory		*/#define	CFG_PROMPT		"DH-T960 # "	/* Monitor Command Prompt	*/#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define	CFG_MAXARGS		16		/* max number of command args	*/#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*//* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need *//* it to wrap 100 times (total 1562500) to get 1 sec. */#define	CFG_HZ			1562500/* valid baudrates */#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }/*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below */#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */#ifdef CONFIG_USE_IRQ#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */#endif/*----------------------------------------------------------------------- * Physical Memory Map */#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */#define CFG_FLASH_BASE		PHYS_FLASH_1/*----------------------------------------------------------------------- * FLASH and environment organization */#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */#if 0#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */#endif#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */#ifdef CONFIG_AMD_LV800#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */#endif#ifdef CONFIG_AMD_LV400#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */#endif/* timeout values are in ticks */#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */#define	CFG_ENV_IS_IN_FLASH	1#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */#endif	/* __CONFIG_H */#define CONFIG_S3C2410_NAND_BOOT 1#define STACK_BASE    0x33f00000#define STACK_SIZE    0x8000#define UBOOT_RAM_BASE    0x33f80000/* NAND Flash Controller */#define NAND_CTL_BASE            0x4E000000#define bINT_CTL(Nb)        __REG(INT_CTL_BASE + (Nb))/* Offset */#define oNFCONF               0x00#define oNFCMD                0x04#define oNFADDR               0x08#define oNFDATA               0x0c#define oNFSTAT               0x10#define oNFECC                0x14/*----------------------------------------------------------------------- * NAND flash settings * Added by Lu Xianzi 2006.5.27 * Copied from include/conifgs/vcma9.h */#if (CONFIG_COMMANDS & CFG_CMD_NAND)#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices  */#define SECTORSIZE 512#define ADDR_COLUMN 1#define ADDR_PAGE 2#define ADDR_COLUMN_PAGE 3#define NAND_ChipID_UNKNOWN  0x00#define NAND_MAX_FLOORS 1#define NAND_MAX_CHIPS 1#define NAND_WAIT_READY(nand) NF_WaitRB()#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)#define WRITE_NAND(d, adr)  NF_Write(d)#define READ_NAND(adr)   NF_Read()/* the following functions are NOP's because S3C24X0 handles this in hardware */#define NAND_CTL_CLRALE(nandptr)#define NAND_CTL_SETALE(nandptr)#define NAND_CTL_CLRCLE(nandptr)#define NAND_CTL_SETCLE(nandptr)// #define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* This definition above is commented by Lu Xianzi. 2006.05.28   Because there's no definition of a macro called __mem_pci,   there will be a link error. */#define CONFIG_MTD_NAND_ECC_JFFS2 1#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */