?? mx21.h
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//#########################################
//# SDHC1 #
//# $1001_3000 to $1001_3FFF #
//#########################################
#define SDHC1_BASE_ADDR 0x10013000
#define SDHC1_STR_STP_CLK (SDHC1_BASE_ADDR+0x00) // 32bit sdhc1 control reg
#define SDHC1_STATUS (SDHC1_BASE_ADDR+0x04) // 32bit sdhc1 status reg
#define SDHC1_CLK_RATE (SDHC1_BASE_ADDR+0x08) // 32bit sdhc1 clock rate reg
#define SDHC1_CMD_DAT_CONT (SDHC1_BASE_ADDR+0x0C) // 32bit sdhc1 cmd/data control reg
#define SDHC1_RESPONSE_TO (SDHC1_BASE_ADDR+0x10) // 32bit sdhc1 response time out reg
#define SDHC1_READ_TO (SDHC1_BASE_ADDR+0x14) // 32bit sdhc1 read time out reg
#define SDHC1_BLK_LEN (SDHC1_BASE_ADDR+0x18) // 32bit sdhc1 block length reg
#define SDHC1_NOB (SDHC1_BASE_ADDR+0x1C) // 32bit sdhc1 number of blocks reg
#define SDHC1_REV_NO (SDHC1_BASE_ADDR+0x20) // 32bit sdhc1 revision number reg
#define SDHC1_INT_MASK (SDHC1_BASE_ADDR+0x24) // 32bit sdhc1 interrupt mask reg
#define SDHC1_CMD (SDHC1_BASE_ADDR+0x28) // 32bit sdhc1 command code reg
#define SDHC1_ARGH (SDHC1_BASE_ADDR+0x2C) // 32bit sdhc1 argument high reg
#define SDHC1_ARGL (SDHC1_BASE_ADDR+0x30) // 32bit sdhc1 argument low reg
#define SDHC1_RES_FIFO (SDHC1_BASE_ADDR+0x34) // 32bit sdhc1 response fifo reg
#define SDHC1_BUFFER_ACCESS (SDHC1_BASE_ADDR+0x38) // 32bit sdhc1 buffer access reg
//#########################################
//# SDHC2 #
//# $1001_4000 to $1001_4FFF #
//#########################################
#define SDHC2_BASE_ADDR 0x10014000
#define SDHC2_STR_STP_CLK (SDHC2_BASE_ADDR+0x00) // 32bit sdhc2 control reg
#define SDHC2_STATUS (SDHC2_BASE_ADDR+0x04) // 32bit sdhc2 status reg
#define SDHC2_CLK_RATE (SDHC2_BASE_ADDR+0x08) // 32bit sdhc2 clock rate reg
#define SDHC2_CMD_DAT_CONT (SDHC2_BASE_ADDR+0x0C) // 32bit sdhc2 cmd/data control reg
#define SDHC2_RESPONSE_TO (SDHC2_BASE_ADDR+0x10) // 32bit sdhc2 response time out reg
#define SDHC2_READ_TO (SDHC2_BASE_ADDR+0x14) // 32bit sdhc2 read time out reg
#define SDHC2_BLK_LEN (SDHC2_BASE_ADDR+0x18) // 32bit sdhc2 block length reg
#define SDHC2_NOB (SDHC2_BASE_ADDR+0x1C) // 32bit sdhc2 number of blocks reg
#define SDHC2_REV_NO (SDHC2_BASE_ADDR+0x20) // 32bit sdhc2 revision number reg
#define SDHC2_INT_MASK (SDHC2_BASE_ADDR+0x24) // 32bit sdhc2 interrupt mask reg
#define SDHC2_CMD (SDHC2_BASE_ADDR+0x28) // 32bit sdhc2 command code reg
#define SDHC2_ARGH (SDHC2_BASE_ADDR+0x2C) // 32bit sdhc2 argument high reg
#define SDHC2_ARGL (SDHC2_BASE_ADDR+0x30) // 32bit sdhc2 argument low reg
#define SDHC2_RES_FIFO (SDHC2_BASE_ADDR+0x34) // 32bit sdhc2 response fifo reg
#define SDHC2_BUFFER_ACCESS (SDHC2_BASE_ADDR+0x38) // 32bit sdhc2 buffer access reg
//#########################################
//# GPIO #
//# $1001_5000 to $1001_5FFF #
//#########################################
#define GPIOA_BASE_ADDR 0x10015000
#define GPIOA_DDIR (GPIOA_BASE_ADDR+0x00) // 32bit gpio pta data direction reg
#define GPIOA_OCR1 (GPIOA_BASE_ADDR+0x04) // 32bit gpio pta output config 1 reg
#define GPIOA_OCR2 (GPIOA_BASE_ADDR+0x08) // 32bit gpio pta output config 2 reg
#define GPIOA_ICONFA1 (GPIOA_BASE_ADDR+0x0C) // 32bit gpio pta input config A1 reg
#define GPIOA_ICONFA2 (GPIOA_BASE_ADDR+0x10) // 32bit gpio pta input config A2 reg
#define GPIOA_ICONFB1 (GPIOA_BASE_ADDR+0x14) // 32bit gpio pta input config B1 reg
#define GPIOA_ICONFB2 (GPIOA_BASE_ADDR+0x18) // 32bit gpio pta input config B2 reg
#define GPIOA_DR (GPIOA_BASE_ADDR+0x1C) // 32bit gpio pta data reg
#define GPIOA_GIUS (GPIOA_BASE_ADDR+0x20) // 32bit gpio pta in use reg
#define GPIOA_SSR (GPIOA_BASE_ADDR+0x24) // 32bit gpio pta sample status reg
#define GPIOA_ICR1 (GPIOA_BASE_ADDR+0x28) // 32bit gpio pta interrupt ctrl 1 reg
#define GPIOA_ICR2 (GPIOA_BASE_ADDR+0x2C) // 32bit gpio pta interrupt ctrl 2 reg
#define GPIOA_IMR (GPIOA_BASE_ADDR+0x30) // 32bit gpio pta interrupt mask reg
#define GPIOA_ISR (GPIOA_BASE_ADDR+0x34) // 32bit gpio pta interrupt status reg
#define GPIOA_GPR (GPIOA_BASE_ADDR+0x38) // 32bit gpio pta general purpose reg
#define GPIOA_SWR (GPIOA_BASE_ADDR+0x3C) // 32bit gpio pta software reset reg
#define GPIOA_PUEN (GPIOA_BASE_ADDR+0x40) // 32bit gpio pta pull up enable reg
#define GPIOB_BASE_ADDR 0x10015100
#define GPIOB_DDIR (GPIOB_BASE_ADDR+0x00) // 32bit gpio ptb data direction reg
#define GPIOB_OCR1 (GPIOB_BASE_ADDR+0x04) // 32bit gpio ptb output config 1 reg
#define GPIOB_OCR2 (GPIOB_BASE_ADDR+0x08) // 32bit gpio ptb output config 2 reg
#define GPIOB_ICONFA1 (GPIOB_BASE_ADDR+0x0C) // 32bit gpio ptb input config A1 reg
#define GPIOB_ICONFA2 (GPIOB_BASE_ADDR+0x10) // 32bit gpio ptb input config A2 reg
#define GPIOB_ICONFB1 (GPIOB_BASE_ADDR+0x14) // 32bit gpio ptb input config B1 reg
#define GPIOB_ICONFB2 (GPIOB_BASE_ADDR+0x18) // 32bit gpio ptb input config B2 reg
#define GPIOB_DR (GPIOB_BASE_ADDR+0x1C) // 32bit gpio ptb data reg
#define GPIOB_GIUS (GPIOB_BASE_ADDR+0x20) // 32bit gpio ptb in use reg
#define GPIOB_SSR (GPIOB_BASE_ADDR+0x24) // 32bit gpio ptb sample status reg
#define GPIOB_ICR1 (GPIOB_BASE_ADDR+0x28) // 32bit gpio ptb interrupt ctrl 1 reg
#define GPIOB_ICR2 (GPIOB_BASE_ADDR+0x2C) // 32bit gpio ptb interrupt ctrl 2 reg
#define GPIOB_IMR (GPIOB_BASE_ADDR+0x30) // 32bit gpio ptb interrupt mask reg
#define GPIOB_ISR (GPIOB_BASE_ADDR+0x34) // 32bit gpio ptb interrupt status reg
#define GPIOB_GPR (GPIOB_BASE_ADDR+0x38) // 32bit gpio ptb general purpose reg
#define GPIOB_SWR (GPIOB_BASE_ADDR+0x3C) // 32bit gpio ptb software reset reg
#define GPIOB_PUEN (GPIOB_BASE_ADDR+0x40) // 32bit gpio ptb pull up enable reg
#define GPIOC_BASE_ADDR 0x10015200
#define GPIOC_DDIR (GPIOC_BASE_ADDR+0x00) // 32bit gpio ptc data direction reg
#define GPIOC_OCR1 (GPIOC_BASE_ADDR+0x04) // 32bit gpio ptc output config 1 reg
#define GPIOC_OCR2 (GPIOC_BASE_ADDR+0x08) // 32bit gpio ptc output config 2 reg
#define GPIOC_ICONFA1 (GPIOC_BASE_ADDR+0x0C) // 32bit gpio ptc input config A1 reg
#define GPIOC_ICONFA2 (GPIOC_BASE_ADDR+0x10) // 32bit gpio ptc input config A2 reg
#define GPIOC_ICONFB1 (GPIOC_BASE_ADDR+0x14) // 32bit gpio ptc input config B1 reg
#define GPIOC_ICONFB2 (GPIOC_BASE_ADDR+0x18) // 32bit gpio ptc input config B2 reg
#define GPIOC_DR (GPIOC_BASE_ADDR+0x1C) // 32bit gpio ptc data reg
#define GPIOC_GIUS (GPIOC_BASE_ADDR+0x20) // 32bit gpio ptc in use reg
#define GPIOC_SSR (GPIOC_BASE_ADDR+0x24) // 32bit gpio ptc sample status reg
#define GPIOC_ICR1 (GPIOC_BASE_ADDR+0x28) // 32bit gpio ptc interrupt ctrl 1 reg
#define GPIOC_ICR2 (GPIOC_BASE_ADDR+0x2C) // 32bit gpio ptc interrupt ctrl 2 reg
#define GPIOC_IMR (GPIOC_BASE_ADDR+0x30) // 32bit gpio ptc interrupt mask reg
#define GPIOC_ISR (GPIOC_BASE_ADDR+0x34) // 32bit gpio ptc interrupt status reg
#define GPIOC_GPR (GPIOC_BASE_ADDR+0x38) // 32bit gpio ptc general purpose reg
#define GPIOC_SWR (GPIOC_BASE_ADDR+0x3C) // 32bit gpio ptc software reset reg
#define GPIOC_PUEN (GPIOC_BASE_ADDR+0x40) // 32bit gpio ptc pull up enable reg
#define GPIOD_BASE_ADDR 0x10015300
#define GPIOD_DDIR (GPIOD_BASE_ADDR+0x00) // 32bit gpio ptd data direction reg
#define GPIOD_OCR1 (GPIOD_BASE_ADDR+0x04) // 32bit gpio ptd output config 1 reg
#define GPIOD_OCR2 (GPIOD_BASE_ADDR+0x08) // 32bit gpio ptd output config 2 reg
#define GPIOD_ICONFA1 (GPIOD_BASE_ADDR+0x0C) // 32bit gpio ptd input config A1 reg
#define GPIOD_ICONFA2 (GPIOD_BASE_ADDR+0x10) // 32bit gpio ptd input config A2 reg
#define GPIOD_ICONFB1 (GPIOD_BASE_ADDR+0x14) // 32bit gpio ptd input config B1 reg
#define GPIOD_ICONFB2 (GPIOD_BASE_ADDR+0x18) // 32bit gpio ptd input config B2 reg
#define GPIOD_DR (GPIOD_BASE_ADDR+0x1C) // 32bit gpio ptd data reg
#define GPIOD_GIUS (GPIOD_BASE_ADDR+0x20) // 32bit gpio ptd in use reg
#define GPIOD_SSR (GPIOD_BASE_ADDR+0x24) // 32bit gpio ptd sample status reg
#define GPIOD_ICR1 (GPIOD_BASE_ADDR+0x28) // 32bit gpio ptd interrupt ctrl 1 reg
#define GPIOD_ICR2 (GPIOD_BASE_ADDR+0x2C) // 32bit gpio ptd interrupt ctrl 2 reg
#define GPIOD_IMR (GPIOD_BASE_ADDR+0x30) // 32bit gpio ptd interrupt mask reg
#define GPIOD_ISR (GPIOD_BASE_ADDR+0x34) // 32bit gpio ptd interrupt status reg
#define GPIOD_GPR (GPIOD_BASE_ADDR+0x38) // 32bit gpio ptd general purpose reg
#define GPIOD_SWR (GPIOD_BASE_ADDR+0x3C) // 32bit gpio ptd software reset reg
#define GPIOD_PUEN (GPIOD_BASE_ADDR+0x40) // 32bit gpio ptd pull up enable reg
#define GPIOE_BASE_ADDR 0x10015400
#define GPIOE_DDIR (GPIOE_BASE_ADDR+0x00) // 32bit gpio pte data direction reg
#define GPIOE_OCR1 (GPIOE_BASE_ADDR+0x04) // 32bit gpio pte output config 1 reg
#define GPIOE_OCR2 (GPIOE_BASE_ADDR+0x08) // 32bit gpio pte output config 2 reg
#define GPIOE_ICONFA1 (GPIOE_BASE_ADDR+0x0C) // 32bit gpio pte input config A1 reg
#define GPIOE_ICONFA2 (GPIOE_BASE_ADDR+0x10) // 32bit gpio pte input config A2 reg
#define GPIOE_ICONFB1 (GPIOE_BASE_ADDR+0x14) // 32bit gpio pte input config B1 reg
#define GPIOE_ICONFB2 (GPIOE_BASE_ADDR+0x18) // 32bit gpio pte input config B2 reg
#define GPIOE_DR (GPIOE_BASE_ADDR+0x1C) // 32bit gpio pte data reg
#define GPIOE_GIUS (GPIOE_BASE_ADDR+0x20) // 32bit gpio pte in use reg
#define GPIOE_SSR (GPIOE_BASE_ADDR+0x24) // 32bit gpio pte sample status reg
#define GPIOE_ICR1 (GPIOE_BASE_ADDR+0x28) // 32bit gpio pte interrupt ctrl 1 reg
#define GPIOE_ICR2 (GPIOE_BASE_ADDR+0x2C) // 32bit gpio pte interrupt ctrl 2 reg
#define GPIOE_IMR (GPIOE_BASE_ADDR+0x30) // 32bit gpio pte interrupt mask reg
#define GPIOE_ISR (GPIOE_BASE_ADDR+0x34) // 32bit gpio pte interrupt status reg
#define GPIOE_GPR (GPIOE_BASE_ADDR+0x38) // 32bit gpio pte general purpose reg
#define GPIOE_SWR (GPIOE_BASE_ADDR+0x3C) // 32bit gpio pte software reset reg
#define GPIOE_PUEN (GPIOE_BASE_ADDR+0x40) // 32bit gpio pte pull up enable reg
#define GPIOF_BASE_ADDR 0x10015500
#define GPIOF_DDIR (GPIOF_BASE_ADDR+0x00) // 32bit gpio ptf data direction reg
#define GPIOF_OCR1 (GPIOF_BASE_ADDR+0x04) // 32bit gpio ptf output config 1 reg
#define GPIOF_OCR2 (GPIOF_BASE_ADDR+0x08) // 32bit gpio ptf output config 2 reg
#define GPIOF_ICONFA1 (GPIOF_BASE_ADDR+0x0C) // 32bit gpio ptf input config A1 reg
#define GPIOF_ICONFA2 (GPIOF_BASE_ADDR+0x10) // 32bit gpio ptf input config A2 reg
#define GPIOF_ICONFB1 (GPIOF_BASE_ADDR+0x14) // 32bit gpio ptf input config B1 reg
#define GPIOF_ICONFB2 (GPIOF_BASE_ADDR+0x18) // 32bit gpio ptf input config B2 reg
#define GPIOF_DR (GPIOF_BASE_ADDR+0x1C) // 32bit gpio ptf data reg
#define GPIOF_GIUS (GPIOF_BASE_ADDR+0x20) // 32bit gpio ptf in use reg
#define GPIOF_SSR (GPIOF_BASE_ADDR+0x24) // 32bit gpio ptf sample status reg
#define GPIOF_ICR1 (GPIOF_BASE_ADDR+0x28) // 32bit gpio ptf interrupt ctrl 1 reg
#define GPIOF_ICR2 (GPIOF_BASE_ADDR+0x2C) // 32bit gpio ptf interrupt ctrl 2 reg
#define GPIOF_IMR (GPIOF_BASE_ADDR+0x30) // 32bit gpio ptf interrupt mask reg
#define GPIOF_ISR (GPIOF_BASE_ADDR+0x34) // 32bit gpio ptf interrupt status reg
#define GPIOF_GPR (GPIOF_BASE_ADDR+0x38) // 32bit gpio ptf general purpose reg
#define GPIOF_SWR (GPIOF_BASE_ADDR+0x3C) // 32bit gpio ptf software reset reg
#define GPIOF_PUEN (GPIOF_BASE_ADDR+0x40) // 32bit gpio ptf pull up enable reg
#define GPIO_REG_BASE 0x10015600
#define GPIO_PMASK (GPIO_REG_BASE+0x00) // 32bit gpio interrupt mask reg
//#########################################
//# AUDMUX #
//# $1001_6000 to $1001_6FFF #
//#########################################
#define AUDMUX_BASE_ADDR 0x10016000
#define AUDMUX_HPCR1 (AUDMUX_BASE_ADDR+0x00) // 32bit audmux host config reg 1
#define AUDMUX_HPCR2 (AUDMUX_BASE_ADDR+0x04) // 32bit audmux host config reg 2
#define AUDMUX_HPCR3 (AUDMUX_BASE_ADDR+0x08) // 32bit audmux host config reg 3
#define AUDMUX_PPCR1 (AUDMUX_BASE_ADDR+0x10) // 32bit audmux pripheral config 1
#define AUDMUX_PPCR2 (AUDMUX_BASE_ADDR+0x14) // 32bit audmux pripheral config 2
#define AUDMUX_PPCR3 (AUDMUX_BASE_ADDR+0x1C) // 32bit audmux pripheral config 3
//#########################################
//# AIPI2 #
//# $1002_0000 to $1002_0FFF #
//#########################################
#define AIPI2_BASE_ADDR 0x10020000
#define AIPI2_PSR0 (AIPI2_BASE_ADDR+0x00) // 32bit Peripheral Size Reg 0
#define AIPI2_PSR1 (AIPI2_BASE_ADDR+0x04) // 32bit Peripheral Size Reg 1
#define AIPI2_PAR (AIPI2_BASE_ADDR+0x08) // 32bit Peripheral Access Reg
//#########################################
//# LCDC #
//# $1002_1000 to $1002_1FFF #
//#########################################
#define LCDC_BASE_ADDR 0x10021000
#define LCDC_LSSAR (LCDC_BASE_ADDR+0x00) // 32bit lcdc screen start addr reg
#define LCDC_LSR (LCDC_BASE_ADDR+0x04) // 32bit lcdc size reg
#define LCDC_LVPWR (LCDC_BASE_ADDR+0x08) // 32bit lcdc virtual page width reg
#define LCDC_LCPR (LCDC_BASE_ADDR+0x0C) // 32bit lcd cursor position reg
#define LCDC_LCWHBR (LCDC_BASE_ADDR+0x10) // 32bit lcd cursor width/heigh/blink
#define LCDC_LCCMR (LCDC_BASE_ADDR+0x14) // 32bit lcd color cursor mapping reg
#define LCDC_LPCR (LCDC_BASE_ADDR+0x18) // 32bit lcdc panel config reg
#define LCDC_LHCR (LCDC_BASE_ADDR+0x1C) // 32bit lcdc horizontal config reg
#define LCDC_LVCR (LCDC_BASE_ADDR+0x20) // 32bit lcdc vertical config reg
#define LCDC_LPOR (LCDC_BASE_ADDR+0x24) // 32bit lcdc panning offset reg
#define LCDC_LSCR (LCDC_BASE_ADDR+0x28) // 32bit lcdc sharp config 1 reg
#define LCDC_LPCCR (LCDC_BASE_ADDR+0x2C) // 32bit lcdc pwm contrast ctrl reg
#define LCDC_LDCR (LCDC_BASE_ADDR+0x30) // 32bit lcdc dma control reg
#define LCDC_LRMCR (LCDC_BASE_ADDR+0x34) // 32bit lcdc refresh mode ctrl reg
#define LCDC_LICR (LCDC_BASE_ADDR+0x38) // 32bit lcdc interrupt config reg
#define LCDC_LIER (LCDC_BASE_ADDR+0x3C) // 32bit lcdc interrupt enable reg
#define LCDC_LISR (LCDC_BASE_ADDR+0x40) // 32bit lcdc interrupt status reg
#define LCDC_LGWSAR (LCDC_BASE_ADDR+0x50) // 32bit lcdc graphic win start add
#define LCDC_LGWSR (LCDC_BASE_ADDR+0x54) // 32bit lcdc graphic win size reg
#define LCDC_LGWVPWR (LCDC_BASE_ADDR+0x58) // 32bit lcdc graphic win virtual pg
#define LCDC_LGWPOR (LCDC_BASE_ADDR+0x5C) // 32bit lcdc graphic win pan offset
#define LCDC_LGWPR (LCDC_BASE_ADDR+0x60) // 32bit lcdc graphic win positon reg
#define LCDC_LGWCR (LCDC_BASE_ADDR+0x64) // 32bit lcdc graphic win control reg
#define LCDC_LGWDCR (LCDC_BASE_ADDR+0x68) // 32bit lcdc graphic win DMA control reg
#define LCDC_BPLUT_BASE (LCDC_BASE_ADDR+0x800) // Background Plane LUT (800 - BFC)
#define LCDC_GWLUT_BASE (LCDC_BASE_ADDR+0xC00) // Background Plane LUT (C00 - FFC)
//#########################################
//# SLCDC #
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