?? shiftreg_3.vhd
字號:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY shiftreg IS
PORT(Di,clk : IN STD_LOGIC;
Q3,Q2,Q1,Q0 : OUT STD_LOGIC);
END shiftreg;
ARCHITECTURE a OF shiftreg IS
SIGNAL temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
IF clk'event and clk = '1' THEN
temp(3) <= Di;
temp(2)<=temp(3);
temp(1)<=temp(2);
temp(0)<=temp(1);
END IF;
END PROCESS;
Q3 <= temp(3); Q2 <= temp(2); Q1 <= temp(1); Q0 <= temp(0);
END a;
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