Timing Analyzer report for shiftreg
Fri Aug 13 16:28:37 2004
Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Settings
  3. Timing Analyzer Summary
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. th
  9. Minimum tco
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-----------------------------------------------------------------------------------------
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP20K30ETC144-1    ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+--------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                                    ; From      ; To        ;
+------------------------+-------+---------------+------------------------------------------------+-----------+-----------+
; Worst-case tsu         ; N/A   ; None          ; 4.211 ns                                       ; Di        ; Q[3]~reg0 ;
; Worst-case tco         ; N/A   ; None          ; 5.713 ns                                       ; Q[1]~reg0 ; Q[1]      ;
; Worst-case th          ; N/A   ; None          ; -3.649 ns                                      ; Di        ; Q[3]~reg0 ;
; Worst-case minimum tco ; N/A   ; None          ; 4.905 ns                                       ; Q[2]~reg0 ; Q[2]      ;
; Clock Setup: 'clk'     ; N/A   ; None          ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; Q[3]~reg0 ; Q[2]~reg0 ;
+------------------------+-------+---------------+------------------------------------------------+-----------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                         ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period)                           ; From      ; To        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; Q[3]~reg0 ; Q[2]~reg0 ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; Q[1]~reg0 ; Q[0]~reg0 ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; Q[2]~reg0 ; Q[1]~reg0 ; clk        ; clk      ; None                        ; None                      ; None                    ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tsu                                                             ;
+------------------------------------------------------------------
; Slack ; Required tsu ; Actual tsu ; From ; To        ; To Clock ;
+-------+--------------+------------+------+-----------+----------+
; N/A   ; None         ; 4.211 ns   ; Di   ; Q[3]~reg0 ; clk      ;
+-------+--------------+------------+------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+--------------------------------------------------------------------
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+