?? shiftreg.fit.eqn
字號:
--A1L01Q is Q[3]~reg0 at LC5_2_A1
--operation mode is normal
A1L01Q_lut_out = Di;
A1L01Q = DFFE(A1L01Q_lut_out, GLOBAL(clk), , , );
--A1L8Q is Q[2]~reg0 at LC3_2_A1
--operation mode is normal
A1L8Q_lut_out = A1L01Q;
A1L8Q = DFFE(A1L8Q_lut_out, GLOBAL(clk), , , );
--A1L6Q is Q[1]~reg0 at LC6_2_A1
--operation mode is normal
A1L6Q_lut_out = A1L8Q;
A1L6Q = DFFE(A1L6Q_lut_out, GLOBAL(clk), , , );
--A1L4Q is Q[0]~reg0 at LC7_2_A1
--operation mode is normal
A1L4Q_lut_out = A1L6Q;
A1L4Q = DFFE(A1L4Q_lut_out, GLOBAL(clk), , , );
--Di is Di at Pin_3
--operation mode is input
Di = INPUT();
--clk is clk at Pin_95
--operation mode is input
clk = INPUT();
--Q[3] is Q[3] at Pin_111
--operation mode is output
Q[3] = OUTPUT(A1L01Q);
--Q[2] is Q[2] at Pin_110
--operation mode is output
Q[2] = OUTPUT(A1L8Q);
--Q[1] is Q[1] at Pin_113
--operation mode is output
Q[1] = OUTPUT(A1L6Q);
--Q[0] is Q[0] at Pin_109
--operation mode is output
Q[0] = OUTPUT(A1L4Q);
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