?? mpeg2.tan.rpt
字號:
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------+---------------------------------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------+---------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 15.100 ns ; CK2M ; 248m-ts-en:595|74298:357|6 ; -- ; CK8M ; 0 ;
; Worst-case tco ; N/A ; None ; 30.900 ns ; fifo_r_w:584|48m_kunbang:370|w_r_en:368|57 ; DESTEN ; CK8M ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 21.300 ns ; A15 ; D0 ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 11.300 ns ; D1 ; yima:621|145 ; -- ; A10 ; 0 ;
; Clock Setup: 'FP8STB' ; N/A ; None ; 32.68 MHz ( period = 30.600 ns ) ; fifo_r_w:584|48m_kunbang:370|auto_det_chx:370|74374:31|19 ; fifo_r_w:584|48m_kunbang:370|auto_det_chx:370|140 ; FP8STB ; FP8STB ; 0 ;
; Clock Setup: 'CK2M' ; N/A ; None ; 35.34 MHz ( period = 28.300 ns ) ; audio_delay:666|delay_counter:61|lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; audio_delay:666|delay_counter:61|RD_FIFO_OE ; CK2M ; CK2M ; 0 ;
; Clock Setup: 'CK8M' ; N/A ; None ; 40.98 MHz ( period = 24.400 ns ) ; mux_8m:583|74374:636|18 ; 2m_sel_ch:650|auto_det_ch:3|FLAG2 ; CK8M ; CK8M ; 0 ;
; Clock Setup: 'FR8' ; N/A ; None ; 64.94 MHz ( period = 15.400 ns ) ; 718 ; 726 ; FR8 ; FR8 ; 0 ;
; Clock Setup: 'CK4M' ; N/A ; None ; 102.04 MHz ( period = 9.800 ns ) ; fifo_r_w:584|48m_fifo_wr:371|74273:409|15 ; fifo_r_w:584|4dff:270|1 ; CK4M ; CK4M ; 0 ;
; Clock Hold: 'CK8M' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; fifo_r_w:584|48m_kunbang:370|change_det:364|74374:31|14 ; fifo_r_w:584|48m_kunbang:370|change_det:364|74374:90|14 ; CK8M ; CK8M ; 146 ;
; Clock Hold: 'CK2M' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; mux_8m:583|74164:720|10 ; mux_8m:583|74374:712|20 ; CK2M ; CK2M ; 8 ;
; Clock Hold: 'FP8STB' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; fifo_r_w:584|48m_kunbang:370|auto_det_chx:373|140 ; fifo_r_w:584|48m_kunbang:370|change_det:364|95 ; FP8STB ; FP8STB ; 1 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 155 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------+---------------------------------------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPF10K20RC208-3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Minimum tpd to report ; 0 ns ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; Off ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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