?? mpeg2.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "FR8 register 718 register 726 64.94 MHz 15.4 ns Internal " "Info: Clock \"FR8\" has Internal fmax of 64.94 MHz between source register \"718\" and destination register \"726\" (period= 15.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.800 ns + Longest register register " "Info: + Longest register to register delay is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 718 1 REG LC2_C16 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C16; Fanout = 12; REG Node = '718'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 718 } "NODE_NAME" } } { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 856 1472 1536 936 "718" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.900 ns) 2.800 ns 726 2 REG LC1_C13 3 " "Info: 2: + IC(1.900 ns) + CELL(0.900 ns) = 2.800 ns; Loc. = LC1_C13; Fanout = 3; REG Node = '726'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { 718 726 } "NODE_NAME" } } { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 1960 1640 1704 2040 "726" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns ( 32.14 % ) " "Info: Total cell delay = 0.900 ns ( 32.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTA?? 快捷鍵說明
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