//        _WrL3Addr(0x14 + 0);    //DATA0 (000101xx+00)        
        _WrL3Data(0xc4,0);      //1100 0,100  : Extended addr(3bits), 100 
        _WrL3Data(0x91,0);      //100,1 00,01 : DATA0, Enable AGC, 00, input amplifier gain channel 2 (2bits)                                  

//        _WrL3Addr(0x14 + 0);    //DATA0 (000101xx+00)
        _WrL3Data(0xc2,0);      //1100 0,010  : Extended addr(3bits), 010 
//        _WrL3Data(0x4d,0);      //010,0 11,01 : DATA0, MIC Amplifier Gain 9dB, input channel 1 select(input channel 2 off) 
        _WrL3Data(0x59,0);      //010,1 10,01 : DATA0, MIC Amplifier Gain 27dB, input channel 1 select(input channel 2 off)
//        _WrL3Data(0x41,0);      //010,0 00,01 : DATA0, MIC Amplifier Gain -3dB, input channel 1 select(input channel 2 off)
    }

}

//===================================================================
void ChangeDMA2(void)
{
    if(which_Buf)
    {
        rDISRCC2 = (0<<1) + (0<<0);                         //AHB, Increment
        rDISRC2  = (int)(Buf + 0x30);                       //0x31000030~(Remove header)
    }
    else
    {
        rDISRCC2 = (0<<1) + (0<<0);                         //AHB, Increment
        rDISRC2  = (int)(Buf + 0x30+(size/2));              //0x31000030 + size/2~
    }
}

//===================================================================
void IIS_PortSetting(void)
{
//----------------------------------------------------------
//   PORT B GROUP
//Ports  :   GPB4    GPB3   GPB2  
//Signal :  L3CLOCK L3DATA L3MODE
//Setting:   OUTPUT OUTPUT OUTPUT 
//           [9:8]   [7:6}  [5:4]
//Binary :     01  ,   01    01 
//----------------------------------------------------------    
    rGPBUP  = rGPBUP  & ~(0x7<<2) | (0x7<<2);   //The pull up function is disabled GPB[4:2] 1 1100    
    rGPBCON = rGPBCON & ~(0x3f<<4) | (0x15<<4); //GPB[4:2]=Output(L3CLOCK):Output(L3DATA):Output(L3MODE)

//----------------------------------------------------------
//   PORT E GROUP
//Ports  :  GPE4    GPE3   GPE2  GPE1    GPE0 
//Signal : I2SSDO  I2SSDI CDCLK I2SSCLK I2SLRCK 
//Binary :   10  ,   10     10 ,  10      10    
//----------------------------------------------------------
    rGPEUP  = rGPEUP  & ~(0x1f)  | 0x1f;    //The pull up function is disabled GPE[4:0] 1 1111
    rGPECON = rGPECON & ~(0x3ff) | 0x2aa;   //GPE[4:0]=I2SSDO:I2SSDI:CDCLK:I2SSCLK:I2SLRCK

    rGPFUP   = ((rGPFUP   & ~(1<<0)) | (1<<0));     //GPF0
    rGPFCON  = ((rGPFCON  & ~(3<<0)) | (1<<1));     //GPF0=EINT0    
    
    rEXTINT0 = ((rEXTINT0 & ~(7<<0)) | (2<<0));     //EINT0=falling edge triggered  
}

//===================================================================
void _WrL3Addr(U8 data)
{       
    S32 i,j;

    rGPBDAT  = rGPBDAT & ~(L3D | L3M | L3C) | L3C;      //L3D=L, L3M=L(in address mode), L3C=H

    for(j=0;j<4;j++);                   //tsu(L3) > 190ns

      //GPB[4:2]=L3C:L3D:L3M
    for(i=0;i<8;i++)                    //LSB first
    {
        if(data & 0x1)                  //If data's LSB is 'H'
        {
            rGPBDAT &= ~L3C;            //L3C=L
            rGPBDAT |= L3D;             //L3D=H             
            for(j=0;j<4;j++);           //tcy(L3) > 500ns
            rGPBDAT |= L3C;             //L3C=H
            rGPBDAT |= L3D;             //L3D=H
            for(j=0;j<4;j++);           //tcy(L3) > 500ns
        }
        else                            //If data's LSB is 'L'
        {
            rGPBDAT &= ~L3C;            //L3C=L
            rGPBDAT &= ~L3D;            //L3D=L
            for(j=0;j<4;j++);           //tcy(L3) > 500ns
            rGPBDAT |= L3C;             //L3C=H
            rGPBDAT &= ~L3D;            //L3D=L
            for(j=0;j<4;j++);           //tcy(L3) > 500ns            
        }
        data >>= 1;
    }
    rGPBDAT  = rGPBDAT & ~(L3D | L3M | L3C) | (L3C | L3M);       //L3M=H,L3C=H   
}

//===================================================================
void _WrL3Data(U8 data,int halt)
{
    S32 i,j;

    if(halt)
    {
        rGPBDAT  = rGPBDAT & ~(L3D | L3M | L3C) | L3C;   //L3C=H(while tstp, L3 interface halt condition)        
        for(j=0;j<4;j++);                                //tstp(L3) > 190ns
    }

    rGPBDAT  = rGPBDAT & ~(L3D | L3M | L3C) | (L3C | L3M);   //L3M=H(in data transfer mode)        
    for(j=0;j<4;j++);                                        //tsu(L3)D > 190ns

      //GPB[4:2]=L3C:L3D:L3M
    for(i=0;i<8;i++)
    {
        if(data & 0x1)                   //if data's LSB is 'H'
        {
           rGPBDAT &= ~L3C;              //L3C=L
           rGPBDAT |= L3D;               //L3D=H
           for(j=0;j<4;j++);             //tcy(L3) > 500ns
           rGPBDAT |= (L3C | L3D);       //L3C=H,L3D=H
           for(j=0;j<4;j++);             //tcy(L3) > 500ns
        }
        else                             //If data's LSB is 'L'
        {
           rGPBDAT &= ~L3C;              //L3C=L
           rGPBDAT &= ~L3D;              //L3D=L
           for(j=0;j<4;j++);             //tcy(L3) > 500ns
           rGPBDAT |= L3C;               //L3C=H
           rGPBDAT &= ~L3D;              //L3D=L
           for(j=0;j<4;j++);             //tcy(L3) > 500ns
        }
        data >>= 1;                      //For check next bit
    }
    rGPBDAT  = rGPBDAT & ~(L3D | L3M | L3C) | (L3C | L3M);    //L3M=H,L3C=H
}

//===================================================================
void __irq DMA2_Done(void)
{
    ClearPending(BIT_DMA2);     //Clear pending bit

    WrUTXH0('@');
    if(!which_Buf)
        which_Buf = 1;
    else
        which_Buf = 0;
}

//===================================================================
void __irq DMA2_Rec_Done(void)
{
    ClearPending(BIT_DMA2);     //Clear pending bit
    Rec_Done = 1;
}

//===================================================================
void __irq RxInt(void)
{
    rSUBSRCPND = BIT_SUB_RXD0;          //Clear pending bit (Requested)
    rSUBSRCPND;
    ClearPending(BIT_UART0);

    *_temp ++= RdURXH0(); 
}

//===================================================================
void __irq Muting(void)
{
    ClearPending(BIT_EINT0);            //Clear pending bit

    if(mute)    //Mute
    {
        _WrL3Addr(0x14 + 0);            //DATA0 (000101xx+00)
        _WrL3Data(0xa4,0);              //10,1,00,1,00 : after, no de-emp, mute, flat 
        mute = 0;
        Uart_Printf("= Mute =\n");
    }
    else        //No mute
    {
        _WrL3Addr(0x14 + 0);            //DATA0 (000101xx+00)
        _WrL3Data(0xa0,0);              //10,1,00,0,00 : after, no de-emp, no mute, flat 
        mute = 1;
        Uart_Printf("= No Mute =\n");
    }
}

//=======[ Added Slave mode Test Program as Bellow --> July 24, 2002 Tark, SOP ]=====

volatile int Tx_Done;
volatile int Rx_Done;

void __irq TR_Done(void)
{
    ClearPending(BIT_DMA2);     //Clear pending bit

    Rx_Done = 1;
    Tx_Done = 1;
//    WrUTXH0('.');
}

//===================================================================
void Iis_Tx(void)
{
    unsigned int i, j;
    unsigned short *txdata;

    Tx_Done = 0;
    Uart_TxEmpty(0);

    Uart_Printf("[ IIS Slave Tx test ]\n");

    IIS_PortSetting();

      //Tx DATA initialize 
    txdata = (unsigned short *)0x31000000;
    
    for(i=0;i<DataCount;i++)
        *(txdata+i) = i;    

      //IIS Initialize
      //Slave[8],Tx[7:6],L-ch=low[5],MSB[4],16bit ch[3],CDCLK[2]=256fs,IISCLK[1:0]=32fs
    rIISMOD  = (1<<8) + (2<<6) + (0<<5) + (1<<4) + (1<<3) + (0<<2) + (1<<0);
    rIISPSR  = (2<<5) + 2;              //Prescaler_A/B=2 <- FCLK 135.4752MHz(1:2:4),11.2896MHz(256fs),44.1KHz
    rIISFCON = (0<<15) + (1<<13);       //Tx Normal[15],Tx FIFO Enable[13] --> start piling....  
      //Tx DMA disable[5],Rx DMA disable[4],Tx not idle[3],Rx idle[2],prescaler enable[1],stop[0]
    rIISCON  = (0<<5) + (0<<4) + (0<<3) + (1<<2) + (1<<1) + (0<<0);            
   
      //Tx start
    rIISCON |=0x1;
    
    for(i=0;i<DataCount;i++)
    {
        while( (rIISCON & 0x080) == 0x80 );     //wait when fifo is not empty.
        *IISFIFO = *(txdata+i);                 // put the data into fifo        
    }

      //Tx Stop(Slave)
    Delay(10);
    rIISCON     = 0x0;          //IIS stop
    rDMASKTRIG2 = (1<<2);       //DMA2 stop
    rIISFCON    = 0x0;          //for FIFO flush

    Uart_Printf("\nTx End...\n");

    Uart_Printf("Last 256 Half-Word in 65KBytes transferred data\n");
    
    for(i=0;i<DataDisplay;i++)
    {
        Uart_Printf("0x%x=",(txdata+0xff00+i));
        Uart_Printf("%04x   ",*(txdata+0xff00+i));        
    }
}
  
//===================================================================
void Iis_Rx(void)
{
    unsigned int i, j, k, count;
    unsigned short *rxdata;

    Rx_Done = 0;
    Uart_TxEmpty(0);

#if PollMode
    Uart_Printf("[ IIS Master Rx Polling mode test ]\n");
#endif

#if DMA2Mode
    Uart_Printf("[ IIS Master Rx DMA2 mode test ]\n");
#endif
    
    IIS_PortSetting();

    pISR_DMA2= (unsigned)TR_Done;
    rINTMSK  = ~(BIT_DMA2);

      //Rx Buf initialize
    rxdata=(unsigned short *)0x31000000;
    
    for(i=0;i<DataCount;i++)
        *(rxdata+i)=0x0;
        
#if DMA2Mode
      //DMA2 Initialize
    rDISRCC2 = (1<<1) + (1<<0);     //The source is in the system bus(APB), address Fixed
    rDISRC2  = ((U32)IISFIFO);      //Base address (start address) of source to transfer(IISFIFO)
    rDIDSTC2 = (0<<1) + (0<<0);     //The destination is in the system bus (AHB), address Increment.
    rDIDST2  = (int)rxdata;         //Base address (start address) of destination to transfer(0x31000000)
    rDCON2   = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(1<<24)+(1<<23)+(1<<22)+(1<<20)+(DataCount);
      //Handshake[31], sync PCLK[30], TC int[29], single tx[28], single service[27], I2SSDI[24], I2S request[23], 
      //off-reload[22], half-word[20], Initial transfer count=DataCount      
    rDMASKTRIG2 = (0<<2)+(1<<1)+0;  //No-stop, DMA2 channel on, No-sw trigger 
 
      //IIS Initialize (DMA Mode)
      //Master[8],Rx[7:6],L-ch=low[5],MSB[4],16bit ch[3],CDCLK[2]=256fs,IISCLK[1:0]=32fs
    rIISMOD  = (0<<8) + (1<<6) + (0<<5) + (1<<4) + (1<<3) + (0<<2) + (1<<0);
    rIISPSR  = (2<<5) + 2;            //Prescaler_A/B=2 <- FCLK 135.4752MHz(1:2:4),11.2896MHz(256fs),44.1KHz
    rIISFCON = (1<<14) + (1<<12);     //Rx DMA[14],Rx FIFO Enable[12]--> start piling....    
      //Tx DMA disable[5],Rx DMA enable[4],Tx idle[3],Rx not idle[2],prescaler enable[1],stop[0]
    rIISCON  = (0<<5) + (1<<4) + (1<<3) + (0<<2) + (1<<1) + (0<<0);    
#endif

#if PollMode
      //IIS Initialize (Polling Mode)
      //Master[8],Rx[7:6],L-ch=low[5],MSB[4],16bit ch[3],CDCLK[2]=256fs,IISCLK[1:0]=32fs
    rIISMOD  = (0<<8) + (1<<6) + (0<<5) + (1<<4) + (1<<3) + (0<<2) + (1<<0);
    rIISPSR  = (2<<5) + 2;            //Prescaler_A/B=2 <- FCLK 135.4752MHz(1:2:4),11.2896MHz(256fs),44.1KHz
    rIISFCON = (0<<14) + (1<<12);     //Rx normal[14],Rx FIFO Enable[12]--> start piling.... 
      //Tx DMA disable[5],Rx DMA disable[4],Tx idle[3],Rx not idle[2],prescaler enable[1],stop[0]
    rIISCON  = (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<1) + (0<<0);    
#endif

      //Rx start
    rIISCON |= 0x1;

#if PollMode       //*** Need to Polling mode ***
    count = DataCount;                 
    while(0<count) 
    {
        j = rIISFCON & 0x1f;            //Rx FIFO data count(Read only)=31
        if(j == 0)
        {
            while(!j)
                j = rIISFCON & 0x1f;    //Rx FIFO data count(Read only)=31
         }
        
        for(i=0;i<j;i++)
        {
            count--;
            *rxdata++ = *IISFIFO;                   
        }
    }
#endif    

#if DMA2Mode  
    while(!Rx_Done);
#endif

      //Rx Stop(Master)
    Delay(10);
    rIISCON     = 0x0;          //IIS stop
    rDMASKTRIG2 = (1<<2);       //DMA2 stop
    rIISFCON    = 0x0;          //for FIFO flush

    Uart_Printf("Last 256 Half-Word in 65KBytes received data\n");

    rxdata=(unsigned short *)0x31000000;  
    
    for(i=0;i<DataDisplay;i++)
    {
        Uart_Printf("0x%x=", (rxdata+0xff00+i));        
        Uart_Printf("%04x   ",*(rxdata+0xff00+i));                
    }
    rINTMSK = (BIT_DMA2);
}