?? armcore9_new.rpt
字號(hào):
23 27 B OUTPUT t 0 0 0 1 0 0 0 nUSB_EN
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:e:\fyp\arm\開發(fā)板資料\cpld 源代碼\armcore9_new.rpt
armcore9_new
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC14 IDE_OE
| +--- LC13 IDE_WE
| | +- LC1 nEXTBUS
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B | Logic cells that feed LAB 'A':
Pin
37 -> - - - | - - | <-- CLKPUT0
43 -> - - * | * - | <-- nGCS0
44 -> - - * | * - | <-- nGCS1
2 -> - - * | * - | <-- nGCS2
3 -> - - * | * - | <-- nGCS3
5 -> * * * | * - | <-- nGCS4
6 -> - - * | * * | <-- nGCS5
35 -> * - - | * * | <-- nOE
39 -> - - - | - * | <-- nRESET
38 -> - * - | * * | <-- nWE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\fyp\arm\開發(fā)板資料\cpld 源代碼\armcore9_new.rpt
armcore9_new
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC18 BUF_DIR
| +--------------- LC28 EXT_CS
| | +------------- LC29 EXT_OE
| | | +----------- LC30 EXT_WE
| | | | +--------- LC26 nIOR_P
| | | | | +------- LC24 nIOW_P
| | | | | | +----- LC23 nMEMR
| | | | | | | +--- LC21 nMEMW
| | | | | | | | +- LC27 nUSB_EN
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B | Logic cells that feed LAB 'B':
Pin
33 -> - - - - * * * * - | - * | <-- ADDR24
37 -> - - - - - - - - - | - - | <-- CLKPUT0
6 -> - * - - - - - - - | * * | <-- nGCS5
35 -> * - * - * - * - - | * * | <-- nOE
39 -> - - - - - - - - * | - * | <-- nRESET
38 -> - - - * - * - * - | * * | <-- nWE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\fyp\arm\開發(fā)板資料\cpld 源代碼\armcore9_new.rpt
armcore9_new
** EQUATIONS **
ADDR24 : INPUT;
CLKPUT0 : INPUT;
IDE_RDY : INPUT;
nGCS0 : INPUT;
nGCS1 : INPUT;
nGCS2 : INPUT;
nGCS3 : INPUT;
nGCS4 : INPUT;
nGCS5 : INPUT;
nOE : INPUT;
nRESET : INPUT;
nWAIT : INPUT;
nWE : INPUT;
nXDACK0 : INPUT;
nXDREQ0 : INPUT;
test1 : INPUT;
test2 : INPUT;
-- Node name is 'BUF_DIR'
-- Equation name is 'BUF_DIR', location is LC018, type is output.
BUF_DIR = LCELL( nOE $ GND);
-- Node name is 'EXT_CS'
-- Equation name is 'EXT_CS', location is LC028, type is output.
EXT_CS = LCELL( nGCS5 $ GND);
-- Node name is 'EXT_OE'
-- Equation name is 'EXT_OE', location is LC029, type is output.
EXT_OE = LCELL( nOE $ GND);
-- Node name is 'EXT_WE'
-- Equation name is 'EXT_WE', location is LC030, type is output.
EXT_WE = LCELL( nWE $ GND);
-- Node name is 'IDE_OE'
-- Equation name is 'IDE_OE', location is LC014, type is output.
IDE_OE = LCELL( _EQ001 $ VCC);
_EQ001 = !nGCS4 & !nOE;
-- Node name is 'IDE_WE'
-- Equation name is 'IDE_WE', location is LC013, type is output.
IDE_WE = LCELL( _EQ002 $ VCC);
_EQ002 = !nGCS4 & !nWE;
-- Node name is 'nEXTBUS'
-- Equation name is 'nEXTBUS', location is LC001, type is output.
nEXTBUS = LCELL( _EQ003 $ GND);
_EQ003 = nGCS0 & nGCS1 & nGCS2 & nGCS3 & nGCS4 & nGCS5;
-- Node name is 'nIOR_P'
-- Equation name is 'nIOR_P', location is LC026, type is output.
nIOR_P = LCELL( _EQ004 $ VCC);
_EQ004 = ADDR24 & !nOE;
-- Node name is 'nIOW_P'
-- Equation name is 'nIOW_P', location is LC024, type is output.
nIOW_P = LCELL( _EQ005 $ VCC);
_EQ005 = ADDR24 & !nWE;
-- Node name is 'nMEMR'
-- Equation name is 'nMEMR', location is LC023, type is output.
nMEMR = LCELL( _EQ006 $ VCC);
_EQ006 = !ADDR24 & !nOE;
-- Node name is 'nMEMW'
-- Equation name is 'nMEMW', location is LC021, type is output.
nMEMW = LCELL( _EQ007 $ VCC);
_EQ007 = !ADDR24 & !nWE;
-- Node name is 'nUSB_EN'
-- Equation name is 'nUSB_EN', location is LC027, type is output.
nUSB_EN = LCELL(!nRESET $ GND);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\fyp\arm\開發(fā)板資料\cpld 源代碼\armcore9_new.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX3000A' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 2,680K
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